W42C31-04
5
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-
µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-
µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
The 6-pF XTAL load capacitors can be used to raise the inte-
grated 17-pF capacitance up to a total load of 20 pF on the
crystal.
Recommended Board Layout
Figure 5 shows a recommended 2-layer board layout.
Document #: 38-00801
Figure 4. Recommended Circuit Configuration
GND
8
7
6
5
1
2
3
4
C1
C2
XTAL1
Output
6 pF
6 pF
R1
C3
FB
C4
5V System Supply
10 µF Tantalum
VDD
0.1 µF
Ordering Information
Ordering Code
Freq. Mask
Code
Package
Name
Package Type
W42C31
04
G
8-pin Plastic SOIC (150-mil)
Figure 5. Recommended Board Layout (2-Layer Board)
C1
C2
Optional Guard Ring for
XTAL Oscillator Circuitry
Clock Output
XTAL1
is not required for operation).
Typical value is 6 pF.
High frequency supply decoupling
capacitor (0.1-µF recommended).
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
XTAL load capacitors (optional; use
FB
Ferrite Bead
C1, C2 =
C3 =
C4 =
Match value to line impedance
R1 =
=
R1
C3
C4
G
G
G
G
G
G
FB
Power Supply Input
(5V)
=
Via To GND Plane
G
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