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W42C31-03 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # W42C31-03
Description  Spread Spectrum Frequency Timing Generator
Download  6 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

W42C31-03 Datasheet(HTML) 3 Page - Cypress Semiconductor

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W42C31-03
3
Spread Spectrum Frequency Timing
Generation
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.
Contrast the typical clock EMI with the Cypress Spread Spec-
trum Frequency Timing Generation EMI. Notice the spike in
the typical clock. This spike can make systems fail quasi-peak
EMI testing. The FCC and other regulatory agencies test for
peak emissions. With spread spectrum enabled, the peak en-
ergy is much lower (at least 8 dB) because the energy is
spread out across a wider bandwidth.
Modulating Waveform
The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in Figure 3. The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
fCenter ± XMOD% in the frequency spread selection table.
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
proach is fMAX XMOD%. Whenever this expression is used,
Cypress has taken care to ensure that fMAX will never be ex-
ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
OE# Pin
An internal pull-down resistor defaults the chip into a mode in
which all outputs are active. If OE# goes HIGH, all outputs are
three-stated. The chip will not prevent short cycles in a transi-
tion from three-state to enabled.
SSFTG
Typical Clock
5dB/div
Figure 2. Typical Clock and SSFTG Comparison
100%
60%
20%
80%
40%
0%
–20%
–40%
–60%
–80%
–100%
Time
Figure 3. Modulation Waveform Profile


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