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CS4953-CL Datasheet(PDF) 21 Page - Cirrus Logic |
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CS4953-CL Datasheet(HTML) 21 Page - Cirrus Logic |
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21 / 44 page  CS4952/53 DS223PP2 21 261 262 1 2 3 4 56 78 9 Start of VSYNC 10 22 Field 1 Burst begins with positive half-cycle Burst begins with negative half-cycle Burst phase = reference phase = 180 relative to B-Y 0 Burst phase = reference phase = 180 relative to B-Y 0 262 263 1 2 3 4 56 78 9 10 22 261 262 1 2 3 4 56 78 9 10 22 262 263 1 2 3 4 56 78 9 10 22 Field 2 Field 3 Field 4 Start of VSYNC Figure 12. NTSC Video Non-Interlaced Progressive Scan Timing Composite Video V[7:0] Active Video Y Cr Y FF 10 XY 00 EAV Code 4 Clocks 00 80 10 80 10 80 10 80 80 10 80 10 80 10 FF XY 00 00 Cb Y Cr Cb Y Cr Ancilliary Data 268 Clocks (NTSC) 280 Clocks (PAL) Horizontal Blanking SAV Code 4 Clocks Active Video 1440 Clocks CCIR656 DATA Figure 13. CCIR656 Input Mode Timing |
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