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CS4630-CM Datasheet(PDF) 8 Page - Cirrus Logic |
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CS4630-CM Datasheet(HTML) 8 Page - Cirrus Logic |
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8 / 38 page  CS4630 8 DS445PP1 AC ’97 SERIAL INTERFACE TIMING (T A = 0 to 70° C; PCIVDD = CRYVDD = 3.3 V; CVDD = 2.5 V;VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V; unless otherwise noted) Parameter Symbol Min Typ Max Unit ABITCLK/ABITCLK2 cycle time taclk 78 81.4 - ns ABITCLK/ABITCLK2 rising to ASDOUT/ADSOUT2 valid tpd5 -17 25 ns ASDIN/ASDIN2 valid to ABITCLK/ABITCLK2 falling ts5 10 - - ns ASDIN/ASDIN2 hold after ABITCLK/ABITCLK2 falling th5 5- - ns PCICLK rising to ARST#/ARST2# valid tpd6 -10 - ns PCICLK taclk pd5 h5 pd6 t t t t s5 Figure 3. AC ’97 Configuration Timing Diagram ABITCLK/ABITCLK2 ASYNC/ASYNC2 ASDOUT/ASDOUT2 ASDIN/ASDIN2 ARST#/ARST2# |
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