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CS43L43-KZ Datasheet(PDF) 4 Page - Cirrus Logic

Part # CS43L43-KZ
Description  Low Voltage,Stereo DAC With Headphone Amp
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L43-KZ Datasheet(HTML) 4 Page - Cirrus Logic

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CS43L43
4
DS479PP3
1.0 PIN DESCRIPTION
Pin Name
#
Pin Description
LRCK
1
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SDATA
2
Serial Audio Data (Input) - Input for two’s complement serial audio data.
SCLK
3
Serial Clock (Input) - Serial clock for the serial audio interface.
DEM
3
De-emphasis Control (Input) - Selects the standard 15
µs/50µs digital de-emphasis filter
response for 44.1 kHz sample rates.
VL
4
Logic Power (Input) - Positive power for the serial audio & control port interface.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VQ_HP
7
Headphone Quiescent Voltage (Output) - Filter connection for internal headphone amp quies-
cent reference voltage.
REF_GND
8
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
9
Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir-
cuits.
HP_A
HP_B
10
14
Headphone Outputs (Output) - The full-scale analog headphone output level is specified in the
Analog Characteristics table.
GND
11
Ground (Input) - Ground reference.
VA
12
Power (Input) - Positive power for the analog & digital sections.
VA_HP
13
Headphone Amp Power (Input) - Positive power for the headphone amplifier.
RST
16
Reset (Input) - Powers down device and resets registers to default conditions when enabled.
Stand-Alone
Definitions
DIF0
DIF1
6
15
Digital Interface Format (Input) - Defines the required relationship between the Left Right
Clock, Serial Clock, and Serial Audio Data.
Control Port
Definitions
SCL
6
Serial Control Port Clock (Input) - Serial clock for the control port interface.
SDA
15
Serial Control Data I/O (Input/Output) - Input/Output for I2C data.
LRCK
RST
SDATA
DIF1/SDA
SCLK/DEM
HP_B
VL
VA_HP
MCLK
VA
DIF0/SCL
GND
VQ_HP
HP_A
REF_GND
FILT+
1
2
3
4
5
6
7
8
5
1
2
6
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
1
2
6
16
15
14
13
12
11
10
9


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