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CS43L43-KZ Datasheet(PDF) 12 Page - Cirrus Logic

Part # CS43L43-KZ
Description  Low Voltage,Stereo DAC With Headphone Amp
Download  36 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L43-KZ Datasheet(HTML) 12 Page - Cirrus Logic

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CS43L43
12
DS479PP3
3.7 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS43L43 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power
arrangements, with VA, VA_HP & VL connected to clean supplies. If the ground planes are split between
digital ground and analog ground, the GND pins of the CS43L43 should be connected to the analog ground
plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwant-
ed coupling into the modulators. The CDB43L43 evaluation board demonstrates the optimum layout and
power supply arrangements.
Notes: The headphone outputs may clip when the value of VA_HP is below VA. It is recommended that these two
supplies be tied together.
3.7.1 Capacitor Placement
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capac-
itor being the closest. The FILT+ and VQ decoupling capacitors must be positioned to minimize the
electrical path from FILT+ to REF_GND (and VQ to REF_GND). To further minimze impedance,
these capacitors should be located on the same layer as the DAC.
3.8 Control Port Interface
The control port is used to load all the internal register settings. Data is clocked into and out of the bi-di-
rectional serial control data line, SDA, by the serial control port clock, SCL (see Figure 8 for the clock to
data relationship). The operation of the control port may be completely asynchronous with the audio sam-
ple rate. However, to avoid potential interference problems, the control port pins should remain static if no
operation is required.
Notes: LRCK & MCLK must always be applied to pins 1 & 5, respectively, during any communication with the
control port.
3.8.1 Enabling the Control Port
The control port pins are shared with the stand-alone configuration pins. To dedicate these pins to
control port functionality, enable the control port prior to the completion of the stand-alone power up
sequence (see section 3.5 for the Recommended Power-up Sequence). To enable the control port,
write 1 to the CP_EN bit using the I2C protocol (see section 3.8.3).
Notes: Setting the CP_EN bit after the Stand-Alone power-up sequence has completed can cause audible
artifacts.
3.8.2 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit
(also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or
reads. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads
or writes of successive registers.


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