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CS43L43-KZ Datasheet(PDF) 7 Page - Cirrus Logic

Part # CS43L43-KZ
Description  Low Voltage,Stereo DAC With Headphone Amp
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L43-KZ Datasheet(HTML) 7 Page - Cirrus Logic

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CS43L43
DS479PP3
7
3.2.1 Internal Serial Clock Mode
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on the
SCLK pin for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and syn-
chronous with MCLK and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon the
MCLK/LRCK ratio and the Digital Interface Format selection (see Table 4).
The internal serial clock is utilized when de-emphasis control is required. Operation in the Internal
Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; how-
ever, External SCLK mode is the recommended system clocking application.
3.2.2 External Serial Clock Mode
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detect-
ed on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial
Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of
LRCK.
3.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated
in Table 5, and 1 of 7 formats in Control Port mode, as illustrated in Table 14.
3.3.1 Stand-Alone Mode
The desired format is selected via the DIF0 and DIF1 pins. For an illustration of the required rela-
tionship between the LRCK, SCLK and SDATA, see Figures 2-4.
Input
Digital Interface Format Selection
Internal
MCLK/LRCK
Ratio
I2S up to 24
Bits
I2S 16
Bits
Left Justified 24
Bits
Right Justified
24, 20, or 18 Bits
Right Justified
16 Bits
SCLK/LRCK
Ratio
512, 256, 128
XX
32
384, 192
XX
X
X
48
512, 256, 128
XX
X
64
Table 4. Internal SCLK/LRCK Ratio
DIF1
DIF0
DESCRIPTION
FORMAT
FIGURE
00
I2S, up to 24-bit data
02
01
Left Justified, up to 24-bit data
13
10
Right Justified, 24-bit Data
24
11
Right Justified, 16-bit Data
34
Table 5. Digital Interface Format - Stand-Alone Mode


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