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CS4390-KS Datasheet(PDF) 11 Page - Cirrus Logic |
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CS4390-KS Datasheet(HTML) 11 Page - Cirrus Logic |
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11 / 22 page  CS4390 DS264F1 11 Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4390 supports both external and internal serial clock generation modes. External Serial Clock The CS4390 will enter the external serial clock mode if 15 or more high\low transitions are detect- ed on the SCLK pin during any phase of the LRCK period. When this mode is enabled, internal serial clock mode cannot be accessed without returning to the power down mode. Internal Serial Clock In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK. The internal SCLK / LRCK ratio is always 64 and operation in this mode is identical to operation with an external serial clock synchronized with LRCK. The SCLK pin must be connected to DGND for proper operation. The internal serial clock mode is advantageous in that there are situations where improper serial clock routing on the printed circuit board can de- grade system performance. The use of the internal serial clock mode simplifies the routing of the printed circuit board by allowing the serial clock trace to be deleted and avoids possible interference effects. Mute Functions The CS4390 includes an auto-mute function which will initiate a mute if 8192 consecutive 0’s or 1’s are input on both the Left and Right channels. The mute will be released when non-static input data is applied to the DAC. The auto-mute function is use- ful for applications, such as compact disk players, where the idle channel noise must be minimized. This feature is active only if the AUTO_MUTE pin is low and is independent of the status of MUTE_L and MUTE_R. Either channel can also be muted instantaneously with the MUTE_L or MUTE_R. De-Emphasis Implementation of digital de-emphasis requires re- configuration of the digital filter to maintain the fil- ter response shown in Figure 8 at multiple sample rates. The CS4390 is capable of digital de-empha- sis for 32, 44.1 or 48kHz sample rates. Table 3 shows the de-emphasis control inputs for DEM 0 and DEM 1. Table 3. De-Emphasis Filter Selection Initialization, Calibration and Power-Down Upon initial power-up, the DAC enters the power- down mode. The interpolation filters and delta-sig- ma modulators are reset, and the internal voltage reference, one-bit D/A converters and switched-ca- pacitor low-pass filters are powered down. The de- vice will remain in the power-down mode until MCLK and LRCK are presented. Once MCLK and LRCK are detected, MCLK occurrences are count- ed over one LRCK period to determine the MCLK/LRCK frequency ratio. The phase and fre- quency relationship between the two clocks must remain fixed. If during any LRCK this relationship DEM 1 DEM 0 De-emphasis 00 32 kHz 01 44.1 kHz 10 48 kHz 11 OFF Gain dB -10dB 0dB Frequency T2 = 15 µs T1 = 50 µs F1 3.183 kHz F2 10.61 kHz Figure 8. De-emphasis Filter Response |
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