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LNK66K Datasheet(PDF) 3 Page - Power Integrations, Inc. |
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LNK66K Datasheet(HTML) 3 Page - Power Integrations, Inc. |
3 / 24 page Rev. C 03/14 3 www.powerint.com LinkSwitch-HP Figure 4. Pin Configuration. Pin Functional Description BYPASS (BP) Pin: An external bypass capacitor is connected to this pin for the internally generated 5.75 V supply. Based on the connected capacitance determined at start-up, it will provide either auto-restart or latching shutdown option dependant on the fault condition. Please see Table 3. COMPENSATION (CP) Pin: This pin is the output of transconductance amplifier. An RC compensation network on this pin provides control loop compensation. DRAIN (D) Pin: This pin is the high-voltage power MOSFET drain connection. It also provides internal operating current for start-up until output is in regulation. FEEDBACK (FB) Pin: The FEEDBACK pin is used to sense output and input voltage by sensing the auxiliary winding voltage. During MOSFET on-time, the current out of the FEEDBACK pin is sensed to detect the line voltage. During the secondary rectifier conduction time, the feedback voltage is proportional to the output voltage via the turns ratio between the bias and secondary windings. PROGRAM (PD) Pin: This MULTI-FUNCTIONAL pin sets device current limit and optional shutdown delay time extension. During start-up, the internal circuit decodes the current limit based on resistor loaded on the PROGRAM pin. Please see Table 4. It can also be used for optionally extending shutdown delay time by changing the capacitance on the pin. See Figure 6. SOURCE (S) Pin: This pin is the power MOSFET source connection. It is also the ground reference for the BYPASS, FEEDBACK, PROGRAM and COMPENSATION pins. Functional Description A LinkSwitch-HP device monolithically integrates a controller and high-voltage power MOSFET into one package. It has a newly developed analogue control scheme, which enables continuous conduction mode (CCM), primary side regulated (PSR) power supplies up to 90 W without the efficiency limitation of DCM or audible noise. It uses an enhanced peak current mode PWM control scheme with multi-mode operation. The multi-mode control engine uses the error amplifier output signal voltage at the COMPENSATION pin to set the operating peak current and switching frequency to maintain the output voltage in regulation as shown in Figure 5. For COMPENSATION pin voltages lower than V C(MCM) (typ. 1.25 V) the device enters multi-cycle modulation (MCM) with a fixed peak current of 25% of the programmed current limit. Several innovative improvements have been added to the peak current mode control to allow primary side regulated CCM operation with no instability. The device meets less than 30 mW input power with no-load at high-line (LNK67xx families). It also offers extensive built-in features: • External current limit selection. • Optional programmable shutdown delay time extension. • Optional remote On/Off. • Optional fast AC reset. • Primary-side sensed output overvoltage protection (OVP) . • Lost regulation protection during output overload or short-circuit (auto-restart). • Internal current limit over line compensation for constant overload power over line. • High-voltage bus overvoltage sense (line OV) for extended line surge withstand. • High-voltage bus undervoltage sense (line UV) for brown-in/ out protection. • Accurate over-temperature protection (OTP). • Output OVP/OCP/OTP shutdown type selection (hysteretic/ latching). • Optional external latching shutdown input (current threshold) • Cycle-by-cycle current limit control. Regulator/Shunt Voltage Clamp The internal 5.75 V regulator charges the bypass capacitor connected to the BYPASS pin to 5.75 V by drawing a current from DRAIN whenever the power MOSFET is off. When the power MOSFET is on, the device operates from the energy stored in the bypass capacitor. In addition, there is a shunt regulator clamping the bypass at 6.4 V when supply current is provided by a bias winding through an external resistor. This makes the device insensitive to bias winding voltage variations. 12 S 11 S 10 S 9 S 8 S 7 S PD 1 FB 2 CP 3 BP 4 D 6 PI-6564-081412 E Package (eSIP-7C) K Package (eSOP-12B) Exposed Pad (On Bottom) Internally Connected to SOURCE Pin Exposed Pad (Hidden) Internally Connected to SOURCE Pin 7 D 5 S 4 B P 3 C P 2 F B 1 P D 1 PD 2 FB 3 CP 4 BP 6 D S 12 S 11 S 10 S 9 S 8 S 7 V Package (eDIP-12B) Exposed Pad Internally Connected to SOURCE Pin |
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