5

Block Diagram

Q

SS

COMP

LGnd

PGnd

-

+

5 BIT

DAC

Slow Feedback

Maximum

On-Time

Timeout

R

Q

S

COFF

One Shot

PWM

COMP

SS High

Comparator

FAULT

Latch

2.5V

Error

Amplifier

Fast Feedback

-

+

Comparator

-

+

-

+

-

+

-

+

VFFB Low

Comparator

PWM

Comparator

SS Low

Comparator

R

Q

S

Q

R

Q

S

2µA

5V

60µA

Normal

Off-Time

Timeout

Extended

Off-Time

Timeout

Time Out

Timer

(30µs)

Edge Triggered

Off-Time

Timeout

3.90V

3.85V

FAULT

FAULT

GATE(H) = ON

GATE(H) = OFF

PGnd

PWM

Latch

1V

0.7V

Package Pin Description: continued

PACKAGE PIN #

PIN SYMBOL

FUNCTION

16L SO Narrow

A capacitor from this pin to ground sets the time duration for the on

board one shot, which is used for the constant off time architecture.

Fast feedback connection to the PWM comparator. This pin is connect-

ed to the regulator output. The inner feedback loop terminates on time.

Boosted power for the high side gate driver.

10

High FET driver pin capable of 1.5A peak switching current. Internal

taneously.

11

PGnd

High current ground for the IC. The MOSFET drivers are referenced to

this pin. Input capacitor ground and the source of lower FET should be

tied to this pin.

12

Low FET driver pin capable of 1.5A peak switching current.

13

Input power for the IC and low side gate driver.

14

LGnd

Signal ground for the IC. All control circuits are referenced to this pin.

15

COMP

Error amplifier compensation pin. A capacitor to ground should be

provided externally to compensate the amplifier.

16

Error amplifier DC feedback input. This is the master voltage feedback

which sets the output voltage. This pin can be connected directly to the

output or a remote sense trace.