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CS4124 Datasheet(PDF) 4 Page - Cherry Semiconductor Corporation

Part No. CS4124
Description  High Side PWM FET Controller
Download  6 Pages
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Maker  CHERRY [Cherry Semiconductor Corporation]
Homepage  http://www.cherrycorp.com/
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CS4124 Datasheet(HTML) 4 Page - Cherry Semiconductor Corporation

   
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1198
Application Information
Oscillator
The IC sets up a constant frequency triangle wave at the
COSC lead whose frequency is related to the external com-
ponents ROSC and COSC, by the following equation:
Frequency =
The peak and valley of the triangle wave are proportional
to VCC by the following:
VVALLEY = 0.1 × VCC
VPEAK = 0.7 × VCC
This is required to make the voltage compensation function
properly. In order to keep the frequency of the oscillator
constant the current that charges COSC must also vary with
supply. ROSC sets up the current which charges COSC. The
voltage across ROSC is 50% of VCC and therefore:
IROSC = 0.5 ×
IROSC is multiplied by (2) internally and transferred to the
COSC lead. Therefore:
ICOSC = ±
The period of the oscillator is:
T = 2COSC ×
The ROSC and COSC components can be varied to create fre-
quencies over the range of 15Hz to 25kHz. With the sug-
gested values of 93.1kΩ and 470pF for ROSC and COSC , the
nominal frequency will be approximately 20 kHz. IROSC, at
VCC = 14V, will be 66.7 µA. IROSC should not change over a
more than 2:1 ratio and therefore COSC should be changed
to adjust the oscillator frequency.
Voltage Duty Cycle Conversion
The IC translates an input voltage at the CTL lead into a
duty cycle at the OUTPUT lead. The transfer function
incorporates Cherry Semiconductor’s patented Voltage
Compensation method to keep the average voltage and
current across the load constant regardless of fluctuations
in the supply voltage. The duty cycle is varied based upon
the input voltage and supply voltage by the following
equation:
Duty Cycle = 100% ×
An internal DC voltage equal to:
VDC = (1.683 × VCTL) + VVALLEY
is compared to the oscillator voltage to produce the com-
pensated duty cycle. The transfer is set up so that when
VCC = 14V the duty cycle will equal VCTL divided by VREG.
For example at VCC = 14V, VREG = 5V and VCTL = 2.5V, the
duty cycle would be 50% at the output. This would place a
7V average voltage across the load. If VCC then drops to
10V, the IC would change the duty cycle to 70% and hence
keep the average load voltage at 7V.
Figure 1: Voltage Compensation
5V Linear Regulator
There is a 5V, 5mA linear regulator available at the VREG
lead for external use. This voltage acts as a reference for
many internal and external functions. It has a drop out of
approximately 1.5V at room temperature.
Current Sense and Timer
The IC differentially monitors the load current on a cycle
by cycle basis at the ISENSE+ and ISENSE- leads. The differen-
tial voltage across these two leads is amplified internally
and compared to the voltage at the IADJ lead. The gain, AV
is set internally and externally by the following equation:
AV ==
The current limit (ILIM) is set by the external current sense
resistor (RSENSE) placed across the ISENSE+ and ISENSE- ter-
minals and the voltage at the IADJ lead.
ILIM =
×
The RCS resistors and CCS components form a differential
low pass filter which filters out high frequency noise gen-
erated by the switching of the external MOSFET and the
associated lead noise. RCS also forms and error term in the
gain of the ILIM equation because the ISENSE+ and ISENSE-
leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50µA while
the chip is in run mode. IADJ should be biased between 1V
and 4V. When the current through the external MOSFET
VI(ADJ)
RSENSE
1000 + RCS
37000
37000
1000 + RCS
VI(ADJ)
ISENSE+ - ISENSE-
120%
100%
80%
60%
40%
20%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
CTL Voltage (% of VREG)
VCC = 8V
VCC = 14V
VCC = 16V
2.8 × VCTL
VCC
VPEAK - VVALLEY
ICOSC
VCC
ROSC
VCC
ROSC
0.83
ROSC × COSC
Theory Of Operation


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