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UC3842B Datasheet(PDF) 10 Page - Motorola, Inc

Part # UC3842B
Description  HIGH PERFORMANCE CURRENT MODE CONTROLLERS
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

UC3842B Datasheet(HTML) 10 Page - Motorola, Inc

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UC3842B, 43B UC2842B, 43B
10
MOTOROLA ANALOG IC DEVICE DATA
Undervoltage Lockout
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The Vref comparator upper
and lower thresholds are 3.6 V/3.4 V. The large hysteresis
and low startup current of the UCX842B makes it ideally
suited in off–line converter applications where efficient
bootstrap startup techniques are required (Figure 33). The
UCX843B is intended for lower voltage dc–to–dc converter
applications. A 36 V zener is connected as a shunt regulator
from VCC to ground. Its purpose is to protect the IC from
excessive voltage that can occur during system startup. The
minimum operating voltage (VCC) for the UCX842B is 11 V
and 8.2 V for the UCX843B.
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to
±1.0 A peak drive current and
has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
The SO–14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the Ipk(max) clamp
level. The separate VC supply input allows the designer
added flexibility in tailoring the drive voltage independent of
VCC. A zener clamp is typically connected to this input when
driving power MOSFETs in systems where VCC is greater
than 20 V. Figure 25 shows proper power and control ground
connections in a current–sensing power MOSFET
application.
Reference
The 5.0 V bandgap reference is trimmed to
±1.0%
tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short–
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse–width jitter. This is usually caused by excessive noise
pick–up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1
µF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout. This
provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
possible using heavy copper runs to minimize radiated EMI.
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other
noise–generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 19A
shows the phenomenon graphically. At t0, switch conduction
begins, causing the inductor current to rise at a slope of m1.
This slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m2,
until the next oscillator cycle. The unstable condition can be
shown if a perturbation is added to the control voltage,
resulting in a small
∆I (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn–on (t2) is increased by ∆I + ∆I m2/m1.
The minimum current at the next cycle (t3) decreases to (∆I +
∆I m2/m1) (m2/m1). This perturbation is multiplied by m2/m1
on each succeeding cycle, alternately increasing and
decreasing the inductor current at switch turn–on. Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If
m2/m1 is greater than 1, the converter will be unstable. Figure
19B shows that by adding an artificial ramp that is
synchronized with the PWM clock to the control voltage, the
∆I perturbation will decrease to zero on succeeding cycles.
This compensating ramp (m3) must have a slope equal to or
slightly greater than m2/2 for stability. With m2/2 slope
compensation, the average inductor current follows the
control voltage, yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense
inputs (Figure 32).
Control Voltage
Inductor
Current
Oscillator Period
Control Voltage
Inductor
Current
Oscillator Period
(A)
(B)
Figure 19. Continuous Current Waveforms
m1
m2
t0
t1
t2
t3
m3
m2
t4
t5
t6
∆I
m1
∆I
Dl ) Dl m2
m1
Dl ) Dl m2
m1
m2
m1


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