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OPA2320SAIDGST Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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OPA2320SAIDGST Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 37 page OPA320, OPA2320 OPA320S, OPA2320S SBOS513E – AUGUST 2010 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS: VS = +1.8V to +5.5V or ±0.9V to ±2.75V (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 10kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN x = VS+, unless otherwise noted. OPA320, OPA320S, OPA2320, OPA2320S PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT RL = 10kΩ 10 20 mV Voltage output swing from VO both rails RL = 2kΩ 25 35 mV RL = 10kΩ 30 mV Over temperature RL = 2kΩ 45 mV Short-circuit current ISC VS = 5.5V ±65 mA Capacitive load drive CL See Typical Characteristics Open-loop output resistance RO IO = 0mA, f = 1MHz 90 Ω SHUTDOWN(3) All amplifiers disabled, SHDN = V– 0.1 0.5 μA Quiescent current per amplifier IQSD OPA2320S only, SHDN A = VS–, SHDN B = VS+ 1.6 mA OPA2320S only, SHDN A = VS+, SHDN B = VS– 1.6 mA High-level input voltage VIH Amplifier enabled, VS– + 0.7 [(VS+) + |VS–|] 0.7 × VS+ 5.5 V Low-level input voltage VIL Amplifier disabled, VS– + 0.3 [(VS+) + |VS–|] 0.3 × VS+ V G = 1, VOUT = 0.1 × VS/2, full shutdown (5) 20 μs Amplifier enable time(4) tON OPA2320S only, partial shutdown(5) 6 Amplifier disable time(4) tOFF G = 1, VOUT = 0.1 × VS/2 3 μs VIH = 5V 0.13 μA SHDN pin input bias current (per pin) VIL = 0V 0.04 μA POWER SUPPLY Specified voltage range VS 1.8 5.5 V Quiescent current per amplifier IQ OPA320, OPA320S IO = 0mA, VS = +5.5V 1.5 1.75 mA Over temperature IO = 0mA, VS = +5.5V 1.85 mA OPA2320, OPA2320S IO = 0mA, VS = +5.5V 1.45 1.6 mA Over temperature IO = 0mA, VS = +5.5V 1.7 mA Power-on time V+ = 0V to 5V, to 90% IQ level 28 μs TEMPERATURE Specified range –40 +125 °C Operating range –40 +150 °C (3) Specified by design and characterization; not production tested. (4) Disable time (tOFF) and enable time (tON) are defined as the time between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level. (5) Full shutdown refers to the dual OPA2320S having both A and B channels disabled (SHDN A = SHDN B = VS–). For partial shutdown, only one SHDN pin is exercised; in this mode, the internal biasing and oscillator remain operational and the enable time is shorter. 4 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: OPA320 OPA2320 OPA320S OPA2320S |
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