SLN04G72F1BB1SA-CCRT datasheet(7/17 Pages) ETC2

Part #	SLN04G72F1BB1SA-CCRT

Description	4GB DDR3L ??SDRAM ECC SO-UDIMM

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preliminary

Data Sheet

Rev.0.9

07.06.2013

Swissbit AG

Industriestrasse 4

Fon: +41 (0) 71 913 03 03

www.swissbit.com

Page 7

CH

– 9552 Bronschhofen

Fax: +41 (0) 71 913 03 15

eMail: info@swissbit.com

of 17

IDD Specifications and Conditions

(0°C

≤ TCASE ≤ + 85°C; VDDQ, VDD = +1.283V – 1.45V)

Parameter

& Test Condition

max.

Symbol

12800-CL11

10600-CL9

Unit

OPERATING CURRENT *) :

One device bank Active-Precharge;

tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH

between valid commands;

DQ inputs changing once per clock cycle; Address and

control inputs changing once every two clock cycles

IDD0

360

mA

OPERATING CURRENT *) :

One device bank; Active-Read-Precharge;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between

valid commands; Address inputs changing once every

two clock cycles; Data Pattern is same as IDD4W

IDD1

495

450

mA

PRECHARGE POWER-DOWN

CURRENT:

All device banks idle; Power-down mode;

tCK = tCK (IDD); CKE is LOW; All Control and

Address bus inputs are not changing; DQ’s

are floating at VREF

Fast Exit

IDD2P

135

mA

Slow Exit

135

PRECHARGE QUIET STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All Control and Address bus inputs are not changing;

DQ’s are floating at V

REF

IDD2Q

180

mA

PRECHARGE STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD2N

180

mA

ACTIVE POWER-DOWN CURRENT:

All device banks open; tCK = tCK (IDD); CKE is LOW; All

Control and Address bus inputs are not changing; DQ’s

are floating at VREF (always fast exit)

IDD3P

180

mA

ACTIVE STANDBY CURRENT:

All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD3N

270

mA

OPERATING READ CURRENT:

All device banks open, Continuous burst reads; One

module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),

AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are changing once

every two clock cycles; DQ inputs changing once per

clock cycle

IDD4R

900

765

mA

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