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SGU08G64B1BB2SA-BB[EW]R Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers

Part No. SGU08G64B1BB2SA-BB[EW]R
Description  8192MB DDR3 SDRAM DIMM
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SGU08G64B1BB2SA-BB[EW]R Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers

 
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preliminary
Data Sheet
Rev.0.9
26.03.2013
Swissbit AG
Industriestrasse 4
Fon: +41 (0) 71 913 03 03
www.swissbit.com
Page 1
CH-9552 Bronschhofen
Fax: +41 (0) 71 913 03 15
eMail: info@swissbit.com
of 16
8192MB DDR3 – SDRAM DIMM
240 Pin UDIMM
SGU08G64B1BB2SA-xxR
8GByte in FBGA Technology
RoHS compliant
*) The refresh rate has to be doubled when 85°C<TC<95°C*)
Environmental Requirements:
Operating temperature (ambient)
Standard Grade
0°C to 70°C
E-Grade
0°C to 85°C
W-Grade
-40°C to 85°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Options:
Data Rate / Latency
Marking
DDR3 1066 MT/s CL7
-BB
DDR3 1333 MT/s CL9
-CC
DDR3 1600 MT/s CL11
-DC
Module Density
8192MB with 16 dies and 2 ranks
Standard Grade
(TA)
0°C to 70°C
(TC)
0°C to 85°C
E-Grade
(TA)
0°C to 85°C
(TC)
0°C to 95°C
W-Grade
(TA)
-40°C to 85°C
(TC)
-40°C to 95°C
Figure: mechanical dimensions
1
Features:
240-pin 64-bit DDR3 Dual-In-Line Double Data Rate
Synchronous DRAM module for industrial applications
Module organization: dual rank 1G x 64
VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V
1.5V I/O ( SSTL_15 compatible)
serial presence-detect (SPD) EEPROM
This module is fully pin and functional compatible to the
JEDEC PC3-12800 spec. and JEDEC- Standard MO-269.
(see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
DDR3 - SDRAM component Samsung K4B4G0846B
512Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit pre-fetch architecture
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
Refresh. Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write Leveling
and Multi Purpose Register (MPR) Read Pattern.
1
if no tolerances specified ± 0.15mm


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