Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

SGU08G64B1BB2SA-BB[EW]R Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers

Part No. SGU08G64B1BB2SA-BB[EW]R
Description  8192MB DDR3 SDRAM DIMM
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ETC [List of Unclassifed Manufacturers]
Homepage  
Logo 

SGU08G64B1BB2SA-BB[EW]R Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers

Zoom Inzoom in Zoom Outzoom out
 9 / 16 page
background image
preliminary
Data Sheet
Rev.0.9
26.03.2013
Swissbit AG
Industriestrasse 4
Fon: +41 (0) 71 913 03 03
www.swissbit.com
Page 9
CH-9552 Bronschhofen
Fax: +41 (0) 71 913 03 15
eMail: info@swissbit.com
of 16
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
12800 CL11
10600 CL9
8500 CL7
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Unit
Clock cycle time
CL = 11
tCK (11)
1.25
1.5
-
-
-
-
ns
CL = 10
tCK (10)
1.5
<1.875
1.5
<1.875
-
-
ns
CL = 9
tCK (9)
1.5
<1.875
1.5
<1.875
-
-
ns
CL = 8
tCK (8)
1.875
<2.5
1.875
<2.5
1.875
<2.5
ns
CL = 7
tCK (7)
1.875
<2.5
1.875
<2.5
1.875
<2.5
ns
CL = 6
tCK (6)
2.5
3.3
2.5
3.3
2.5
3.3
ns
CL = 5
tCK (5)
3.0
3.3
3.0
3.3
3.0
3.3
ns
Read CMD to 1
st data
tAA
13.75
-
13.5
-
13.125
-
ns
CK high-level width
tCH (avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK
CK low-level width
tCL (avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK
Data-out high-impedance
window from CK/CK#
tHZ
-
225
-
250
-
300
ps
Data-out low-impedance window
from CK/CK#
tLZ
-450
225
-500
250
-600
300
ps
DQ and DM input pulse width
( for each input )
tDIPW
360
-
400
-
490
-
ps
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
tQH
0.38
-
0.38
-
0.38
-
tCK
(AVG)
DQS input high pulse width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS input low pulse width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS read preamble
tRPRE
0.9
Note1
0.9
Note1
0.9
Note1
tCK
DQS read postamble
tRPST
0.3
Note2
0.3
Note2
0.3
Note2
tCK
DQS write preamble
tWPRE
0.9
-
0.9
-
0.9
-
tCK
DQS write postamble
tWPST
0.3
-
0.3
-
0.3
-
tCK
1
The maximum preamble is bound by tLZDQS (MAX)
2
The maximum postamble is bound by tHZDQS (MAX)
The DQ, DQS setup and hold times as well as Command/Address setup and hold times need to be calculated using the
respective component data sheets with derating tables and the driver slew rate in combination with the JEDEC min/max
routing information


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn