Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

SGU08G64B1BB2SA-BB[EW]R Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

Part No. SGU08G64B1BB2SA-BB[EW]R
Description  8192MB DDR3 SDRAM DIMM
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ETC [List of Unclassifed Manufacturers]
Homepage  
Logo 

SGU08G64B1BB2SA-BB[EW]R Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers

Zoom Inzoom in Zoom Outzoom out
 7 / 16 page
background image
preliminary
Data Sheet
Rev.0.9
26.03.2013
Swissbit AG
Industriestrasse 4
Fon: +41 (0) 71 913 03 03
www.swissbit.com
Page 7
CH-9552 Bronschhofen
Fax: +41 (0) 71 913 03 15
eMail: info@swissbit.com
of 16
IDD Specifications and Conditions
(0°C
≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
Parameter
& Test Condition
Symbol
max.
Unit
12800 CL11 10600 CL9
8500 CL7
OPERATING CURRENT *) :
One device bank Active-Precharge;
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
IDD0
480
440
440
mA
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address inputs changing once every two
clock cycles; Data Pattern is same as IDD4W
IDD1
560
520
520
mA
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and
Address bus inputs are not changing; DQ’s
are floating at VREF
Fast Exit
IDD2P
240
240
240
mA
Slow Exit
240
240
240
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at V
REF
IDD2Q
320
320
320
mA
PRECHARGE STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
IDD2N
400
400
320
mA
ACTIVE POWER-DOWN CURRENT:
All device banks open; tCK = tCK (IDD); CKE is LOW; All
Control and Address
bus inputs are not changing; DQ’s
are floating at VREF (always fast exit)
IDD3P
320
320
320
mA
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
IDD3N
480
480
480
mA
OPERATING READ CURRENT:
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL
= 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
IDD4R
920
800
680
mA


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn