Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

SGU08G64B1BB2SA-BB[EW]R Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part No. SGU08G64B1BB2SA-BB[EW]R
Description  8192MB DDR3 SDRAM DIMM
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ETC [List of Unclassifed Manufacturers]
Homepage  
Logo 

SGU08G64B1BB2SA-BB[EW]R Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers

Zoom Inzoom in Zoom Outzoom out
 6 / 16 page
background image
preliminary
Data Sheet
Rev.0.9
26.03.2013
Swissbit AG
Industriestrasse 4
Fon: +41 (0) 71 913 03 03
www.swissbit.com
Page 6
CH-9552 Bronschhofen
Fax: +41 (0) 71 913 03 15
eMail: info@swissbit.com
of 16
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
VDD
-0.4
1.975
V
I/O Supply Voltage
VDDQ
-0.4
1.975
V
VDDL Supply Voltage
VDDL
-0.4
1.975
V
Voltage on any pin relative to VSS
VIN, VOUT
-0.4
1.975
V
INPUT LEAKAGE CURRENT
Any input 0V
≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
II
µA
Command/Address
RAS#, CAS#, WE#, S#, CKE
-16
16
CK, CK#
-16
16
DM
-2
2
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)
IOZ
-5
5
µA
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
IVREF
-8
8
µA
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
SYMBOL
MIN
NOM
MAX
UNITS
Supply Voltage
VDD
1.425
1.5
1.575
V
I/O Supply Voltage
VDDQ
1.425
1.5
1.575
V
VDDL Supply Voltage
VDDL
1.425
1.5
1.575
V
I/O Reference Voltage
VREF
0.49 x VDDQ
0.50 x VDDQ
0.51x VDDQ
V
I/O Termination Voltage (system)
VTT
0.49 x VDDQ-20mV
0.50 x VDDQ
0.51x VDDQ+20mV
V
Input High (Logic 1) Voltage
VIH (DC)
VREF + 0.1
VDDQ + 0.3
V
Input Low (Logic 0) Voltage
VIL (DC)
-0.3
VREF – 0.1
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
SYMBOL
MIN
MAX
UNITS
Input High (Logic 1) Voltage
VIH (AC)
VREF + 0.175
-
V
Input Low (Logic 0) Voltage
VIL (AC)
-
VREF - 0.175
V
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn