M25PX16-VMN6TP datasheet(29/65 Pages) NUMONYX

Part #	M25PX16-VMN6TP

Description	16-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface

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Manufacturer	NUMONYX [Numonyx B.V]

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M25PX16

Instructions

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When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W/VPP):

If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has previously been set by a Write

Enable (WREN) instruction.

If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register

even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not

accepted for execution). As a consequence, all the data bytes in the memory area that

are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status

Register, are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected mode (HPM) can be

entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect

(W/VPP) Low

or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write

Protect (W/VPP) High.

If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can

never be activated, and only the Software Protected mode (SPM), using the Block Protect

(BP2, BP1, BP0) bits of the Status Register, can be used.

6.6

Read Data Bytes (READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a

maximum frequency fR, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)

instruction, while an Erase, Program or Write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

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M25PX16-VMN6TP Datasheet(PDF) 29 Page - Numonyx B.V

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