SGU04G64A1BE1MT-DCR datasheet(5/16 Pages) ETC

Part #	SGU04G64A1BE1MT-DCR

Description	4096MB DDR3 ??SDRAM UDIMM

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preliminary

Data Sheet

Rev.0.9

22.07.2013

Swissbit AG

Industriestrasse 4

Fon: +41 (0) 71 913 03 03

www.swissbit.com

Page 5

CH-9552 Bronschhofen

Fax: +41 (0) 71 913 03 15

eMail: info@swissbit.com

of 16

FUNCTIONAL BLOCK DIAGRAMM 4096MB DDR3 SDRAM UDIMM,

1 RANK AND 8 COMPONENTS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

ZQ

D0

DQS

CS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

ZQ

D1

DQS

CS

DQ0

DQ1

DQ2

DQ3

DQ5

DQ4

DQ6

DQ7

S0

DQS0

DM0

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ13

DQ12

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

ZQ

D2

DQS

CS

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ21

DQ20

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

ZQ

D3

DQS

CS

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

ZQ

D4

DQS

CS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

ZQ

D5

DQS

CS

DQ32

DQ33

DQ34

DQ35

DQ37

DQ36

DQ38

DQ39

DQS4

DM4

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ45

DQ44

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

ZQ

D6

DQS

CS

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ53

DQ52

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

ZQ

D7

DQS

CS

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ61

DQ60

DQ62

DQ63

VDDSPD

SPD

VDD/VDDQ

D0-D7

VREFDQ

VREFCA

D0-D7

VSS

BA0-BA2

BA0-BA2: SDRAM D0-D7

A0-A15

A0-A15: SDRAM D0-D7

RAS

RAS: SDRAM D0-D7

CAS

CAS: SDRAM D0-D7

WE

WE: SDRAM D0-D7

ODT0

ODT: SDRAM D0-D7

CKE0

CKE: SDRAM D0-D7

CK0

CK: SDRAM D0-D7

CK0

CK: SDRAM D0-D7

RESET

RESET: SDRAM D0-D7

Notes:

1.

DQ-to-I/O wiring is shown as recommended but may

be changed.

2.

DQ/DQS/DQS/ODT/DM/CKE/S relationship must be

maintained as shown.

3.

DQ, DM, DQS/DQS resistors: Refer to associated

topology diagram.

4.

Refer to the appropriate clock wiring topology under

the DIMM wiring details section of the JEDED document.

5.

For each DRAM, a unique ZQ resistor is connected to

GND. The ZQ resistor is 240

Ω±1%.

6.

Refer to associated figure for SPD details.

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