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S80L186EB16 Datasheet(PDF) 48 Page - InnovASIC, Inc

Part # S80L186EB16
Description  8-Bit/16-Bit Microcontrollers
Download  85 Pages
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Manufacturer  INNOVASIC [InnovASIC, Inc]
Direct Link  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

S80L186EB16 Datasheet(HTML) 48 Page - InnovASIC, Inc

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IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
IA211080314-13
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 48 of 85
1-888-824-4184
4.1.7
I/O Port Unit
The I/O Port Unit (IPU) on the IA186EB/IA188EB supports two 8-bit channels of input, output,
or input/output operation. Port 1 is multiplexed with the chip select pins and is output only.
Most of Port 2 is multiplexed with the serial channel pins.
4.1.8
Refresh Control Unit
The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to
keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks
between refresh requests.
A 12-bit address generator is maintained by the RCU and is presented on the a1–a12 address
lines during the refresh bus cycle. Address Bits [a13–a19] are programmable to allow the refresh
address block to be located on any 8-Kbyte boundary.
4.1.9
Power Management Unit
The IA186EB/IA188EB Power Management Unit (PMU) is provided to control the power
consumption of the device. The PMU provides three power modes: Active, Idle, and
Powerdown.
Active Mode indicates that all units on the IA186EB/IA188EB are functional and the device
consumes maximum power (depending on the level of peripheral operation). Idle Mode freezes
the clocks of the execution and bus units at a logic zero state (all peripherals continue to operate
normally).
The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal
oscillator. All internal registers hold their values provided VCC is maintained. Current
consumption is reduced to just transistor junction leakage.
4.2
Peripheral Architecture
The IA186EB/IA188EB has integrated several common system peripherals with a CPU core to
create a compact, yet powerful system. The integrated peripherals are designed to be flexible
and provide logical interconnections between supporting units (e.g., the interrupt control unit
supports interrupt requests from the timer/counters or serial channels). The list of integrated
peripherals includes:
7-Input Interrupt Control Unit
3-Channel Timer/Counter Unit
2-Channel Serial Communications Unit
10-Output Chip-Select Unit
I/O Port Unit
Refresh Control Unit


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