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S80L186EB16 Datasheet(PDF) 28 Page - InnovASIC, Inc

Part # S80L186EB16
Description  8-Bit/16-Bit Microcontrollers
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Manufacturer  INNOVASIC [InnovASIC, Inc]
Direct Link  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

S80L186EB16 Datasheet(HTML) 28 Page - InnovASIC, Inc

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IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
IA211080314-13
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 28 of 85
1-888-824-4184
Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
Pin
Description
Name
PLCC
LQFP
PQFP
gcs0_n
p1.0/gcs0_n
28
16
59
generic chip select n (n = 0
–7). Output. Active
Low. When programmed and enabled, each of
these pins provide a chip select signal that will
be asserted (low) whenever the address of a
memory or I/O bus cycle is within the address
space programmed for that output.
gcs1_n
p1.1/gcs1_n
27
15
58
gcs2_n
p1.2/gcs2_n
26
14
57
gcs3_n
p1.3/gcs3_n
25
13
56
gcs4_n
p1.4/gcs4_n
24
12
55
gcs5_n
p1.5/gcs5_n
21
9
52
gcs6_n
p1.6/gcs6_n
20
8
51
gcs7_n
p1.7/gcs7_n
19
7
50
hlda
hlda
12
1
44
hold acknowledge. Output. Active High.
When hlda is asserted (high), it indicates that
the IA186EB has relinquished control of the
local bus to another bus master in response to
a HOLD request (see next table entry).
When hlda is asserted, the IA186EB data bus
and control signals float, allowing another bus
master to drive the signals directly.
hold
hold
13
2
45
hold. Input. Active High. This signal is a
request indicating that an external bus master
wishes to gain control of the local bus. The
IA186EB will relinquish control of the local bus
between instruction boundaries not conditioned
by a LOCK prefix.
int0
(input)
int0
(input only)
31
19
62
interrupt n (n = 0-4). Input/Output. Active
High. These maskable inputs interrupt program
flow and cause execution to continue at an
interrupt vector of a specific interrupt type as
follows:
int0: Type 12
int1: Type 13
int2: Type 14
int3: Type 15
int4: Type 17
To allow interrupt expansion, int0 and int1 can
be used with the interrupt acknowledge signals
inta0_n and inta1_n (see next table entries) to
serve as external interrupt inputs or interrupt
acknowledge outputs.
int1
(input)
int1
(input only)
32
20
63
int2
int2/inta0_n
33
21
64
int3
int3/inta1_n
34
22
65
int4
(input)
int4
(input only)
35
23
66
inta0_n
int2/inta0_n
33
21
64
interrupt acknowledge 0. Input/Output. Active
Low. This pin provides an interrupt
acknowledge handshake in response to an
interrupt request on the int0 pin (see previous
table entry).


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