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S80L186EB16 Datasheet(PDF) 26 Page - InnovASIC, Inc

Part # S80L186EB16
Description  8-Bit/16-Bit Microcontrollers
Download  85 Pages
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Manufacturer  INNOVASIC [InnovASIC, Inc]
Direct Link  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

S80L186EB16 Datasheet(HTML) 26 Page - InnovASIC, Inc

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IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
IA211080314-13
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 26 of 85
1-888-824-4184
Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
Pin
Description
Name
PLCC
LQFP
PQFP
ale
ale
6
75
38
address latch enable. Output. Active High.
This signal is used to latch the address
information during the address portion of a bus
cycle.
bclk0
p2.5/bclk0
54
41
4
baud clock, Serial Port 0. Input. The bclk0 pin
can be used to provide an alternate clock
source for Serial Port 0. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
bclk1
p2.2/bclk1
59
46
9
baud clock, Serial Port 1. Input. The bclk1 pin
can be used to provide an alternate clock
source for Serial Port 1. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
bhe_n
bhe_n is
multi-
plexed
with
refresh_n
bhe_n
bhe_n is
multi-
plexed with
refresh_n
7
76
39
byte high enable. Output. Active Low. When
bhe_n is asserted (low), it indicates that the
bus cycle in progress is transferring data over
the upper half of the data bus.
Additionally, bhe_n and ad0 encode the
following bus information:
ad0
bhe_n
Bus Status
0
0
Word Transfer
0
1
Even Byte Transfer
1
0
Odd Byte Transfer
1
1
Refresh Operation
Note: bhe_n is multiplexed with refresh_n.
busy
test_n/busy
14
NA
NA
busy. Input. Active High. When the busy
input is asserted, it causes the IA186EB to
suspend operation during the execution of the
Intel 80C187 Numerics Coprocessor
instructions. Operation resumes when the pin
is sampled low. This applies to the PLCC
package only.


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