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SGL04G72B1BQ2SA-CCRT Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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SGL04G72B1BQ2SA-CCRT Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 18 page Data Sheet Rev.1.0 18.02.2014 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 9 CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18 Parameter & Test Condition Symbol max. Unit 10600-CL9 8500-CL7 OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle IDD4W 963 828 mA BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle IDD5 1188 1143 mA SELF REFRESH CURRENT: CK and CK# at 0V; CKE ≤ 0.2V; All other Control and Address bus inputs are floating at VREF; DQ’s are floating at VREF IDD6 216 216 mA OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle IDD7 1368 1323 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 10600-CL9 8500-CL7 Unit CL (IDD) 9 7 tCK tRCD (IDD) 13.5 13.125 ns tRC (IDD) 49.5 50.625 ns tRRD (IDD) 6 7.5 ns tCK (IDD) 1.5 1.87 ns tRAS MIN (IDD) 36 37.5 ns tRAS MAX (IDD) 70 ’200 70’200 ns tRP (IDD) 13.5 13.125 ns tRFC (IDD) 160 160 ns |
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