SGL04G72B1BD2SA-CCWRT-V datasheet(1/18 Pages) ETC2

Part #	SGL04G72B1BD2SA-CCWRT-V

Description	4096MB DDR3 . SDRAM unbuffered ECC Mini-UDIMM

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Preliminary Data Sheet

Rev.0.9

04.08.2011

Swissbit AG

Industriestrasse 4

Fon: +41 (0) 71 913 03 03

www.swissbit.com

Page 1

CH

– 9552 Bronschhofen

Fax: +41 (0) 71 913 03 15

eMail: info@swissbit.com

of 18

Figure: mechanical dimensions

1

4096MB DDR3 – SDRAM unbuffered ECC Mini-UDIMM

244 Pin ECC Mini-UDIMM

SGL04G72B1BD2SA-CCWRT-V

4GB in FBGA Technology

RoHS compliant

*) The refresh rate has to be doubled when 85°C<TC<95°C

Environmental Requirements:



Operating temperature (ambient)

Standard Grade

0°C to 70°C

W-Grade

-40°C to 85°C



Operating Humidity

10% to 90% relative humidity, noncondensing



Operating Pressure

105 to 69 kPa (up to 10000 ft.)



Storage Temperature

-55°C to 100°C



Storage Humidity

5% to 95% relative humidity, noncondensing



Storage Pressure

1682 PSI (up to 5000 ft.) at 50°C

Options:

 Data Rate / Latency

Marking

DDR3 1333 MT/s CL9

-CC

DDR3 1066 MT/s CL7

-BB

 Module density

4096MB with 18 dies and 2 ranks

 Standard Grade

(TA)

0°C to 70°C

(Tc)

0°C to 85°C

 Grade W

(TA)

-40°C to 85°C

(Tc)

-40°C to 95°C *)

Features:



244-pin 72-bit DDR3 ECC Mini-UDIMM module



Module organization: dual rank 512M x 72



VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V



1.5V I/O ( SSTL_15 compatible)



Fly-by-bus with termination for C/A & CLK bus



On-board I2C temperature sensor with integrated serial

presence-detect (SPD) EEPROM



Gold-contact pad



Dip Coated with HumiSeal 1A33



Coating Thickness 1-3 mils



With anodized aluminum heat spreader



This module is fully pin and functional compatible to the

JEDEC PC3-10600 DDR3 SDRAM Mini-UDIMM design spec.

and JEDEC- Standard MO-244 R/C B. (see www.jedec.org)



The pcb and all components are manufactured according to

the RoHS compliance specification

[EU Directive 2002/95/EC Restriction of Hazardous

Substances (RoHS)]

DDR3 - SDRAM component Samsung K4B2G0846D



256Mx8 DDR3 SDRAM in PG-TFBGA-78 package



8-bit prefetch architecture



Programmable CAS Latency,

CAS Write Latency, Additive

Latency, Burst Length and Burst Type.



On-Die-Termination (ODT) and Dynamic ODT for improved

signal integrity.



Refresh, Self Refresh and Power Down Modes.



ZQ Calibration for output driver and ODT.



System Level Timing Calibration Support via Write Leveling

and Multi Purpose Register (MPR) Read Pattern.

1

if no tolerances specified ± 0.15mm

82.00

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