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NI5751 Datasheet(PDF) 8 Page - National Instruments Corporation

Part No. NI5751
Description  16-Channel, 50 MS/s, 14-Bit Digitizer Adapter Module for NI FlexRIO
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Maker  NI [National Instruments Corporation]
Homepage  http://www.NI.com
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NI5751 Datasheet(HTML) 8 Page - National Instruments Corporation

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NI 5751 FlexRIO CLIP Node Wire Descriptions
NI 5751 CLIP Node IO Descriptions
Port Name
Type
Function
AI A<0..7>
I16
Data from each of the eight channels on ADC A. If you are using the
CLIP, data is clocked out of the CLIP on IO Module Clock 0. If you are
NI 5751
using the
CLIP, data is clocked out of the CLIP on DStarA. After Initialization Done is asserted the data is valid
NI 5751 Multidevice Synchronization
on every clock cycle.
AI
B<8..15>
I16
Data from each of the eight channels on ADC B. If you are using the
CLIP, data is clocked out of the CLIP on IO Module Clock 0. If you are
NI 5751
using the
CLIP, data is clocked out of the CLIP on DStarA. After Initialization Done is asserted the data is valid
NI 5751 Multidevice Synchronization
on every clock cycle.
DI <0..7>
Boolean Digital Input. Refer to the
section for more information.
Digital Input Terminals
DO <0..7>
Boolean Digital Output. Refer to the
section for more information.
Digital Output Terminals
Digital
Output
Enable
Boolean Enables the digital outputs.
IO Module
Clock 0
FPGA
Clock
The ADC sample clock.
Sample
Clock
Select
U8
Selects which clock is used as the ADC sample clock. When Sample Clock Select is changed, the data capture circuit is reinitialized.
This signal
3
should be inside a single-cycle timed loop with a clock source of the 40 MHz onboard clock.
Force
Initialization
Boolean Forces a CLIP initialization. If you are using an external clock and the clock frequency changes, this signal must be manually asserted. ADC registers
3
retain their values when Force Initialization is manually asserted. This signal should be inside a single-cycle timed loop with a clock source of the
40 MHz onboard clock.
Initialization
Done
Boolean When this signal is asserted, initialization of the CLIP has completed. This signal should be inside a single-cycle timed loop with a clock source of the
3
40 MHz onboard clock.


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