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RMLV0416E Datasheet(PDF) 12 Page - Renesas Technology Corp

Part No. RMLV0416E
Description  4Mb Advanced LPSRAM
Download  15 Pages
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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RMLV0416E Datasheet(HTML) 12 Page - Renesas Technology Corp

 
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RMLV0416E Series
R10DS0205EJ0100 Rev.1.00
Page 12 of 13
2014.2.27
Low VCC Data Retention Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test conditions
*27
VCC for data retention
VDR
1.5
V
Vin ≥ 0V,
(1) CS2 ≤ 0.2V
or
(2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V
or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V
Data retention current
ICCDR
0.4
*26
2
A
~+25°C
VCC = 3.0V, Vin ≥ 0V,
(1) CS2 ≤ 0.2V
or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V
or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V
3
A
~+40°C
5
A
~+70°C
7
A
~+85°C
Chip deselect time to data retention
tCDR
0
ns
See retention waveform.
Operation recovery time
tR
5
ms
Note 26. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
27. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB# buffer, UB# buffer and I/O buffer. If
CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, LB#, UB#, I/O) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC-0.2V or CS2 ≤ 0.2V. The
other inputs levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high-impedance state.


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