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R5F64110DFB Datasheet(PDF) 9 Page - Renesas Technology Corp |
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R5F64110DFB Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 102 page R01DS0062EJ0130 Rev.1.30 Page 9 of 93 Mar 3, 2014 R32C/111 Group 1. Overview Figure 1.3 R32C/111 Group Block Diagram for the 64-pin Package Port P0 Port P1 Port P2 Port P3 Port P7 4 3 8 4 8 Peripherals Clock generator: 4 circuits -XIN-XOUT - XCIN-XCOUT - On-chip oscillator - PLL frequency synthesizer X-Y converter: 16 bits × 16 bits CRC calculator (CCITT) X16 + X12 + X5 + 1 Watchdog timer: 15 bits DMAC DMAC II R32C/100 Series CPU Core R2R0 R3R1 R6R4 R7R5 A0 A1 A2 A3 FB SB FLG INTB ISP USP PC SVF SVP VCT Memory ROM RAM Multiplier Floating-point unit R2R0 R3R1 R6R4 R7R5 A0 A1 A2 A3 FB SB D/A converter: 8 bits × 1 channel A/D converter: 10 bits × 1 circuit Standard: 8 inputs Maximum: 20 inputs Timer: Timer A 16 bits × 5 timers Timer B 16 bits × 6 timers Three-phase motor controller Serial interface: 6 channels Intelligent I/O Time measurement: 16 Wave generation: 19 Serial interface: - Variable-length synchronous serial I/O - IEBus Port P6 8 |
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