AD420ANZ-32 datasheet(14/16 Pages) AD | Serial Input 16-Bit 4 mA??0 mA, 0 mA??0 mA DAC

Part No.	AD420ANZ-32

Description	Serial Input 16-Bit 4 mA??0 mA, 0 mA??0 mA DAC

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AD420

Rev. H | Page 14 of 16

AD420 PROTECTION

TRANSIENT VOLTAGE PROTECTION

The AD420 contains ESD protection diodes, which prevent

damage from normal handling. The industrial control envir-

onment can, however, subject I/O circuits to much higher

transients. To protect the AD420 from excessively high voltage

transients, such as those specified in IEC 801, external power

diodes and a surge current limiting resistor may be required, as

shown in Figure 15. The constraint on the resistor is that during

normal operation the output voltage level at IOUT must remain

within its voltage compliance limit

(IOUT × (Rp + RLOAD) ≤ VCC − 2.75 V)

and the two protection diodes and resistor must have

appropriate power ratings.

AD420 I

OUT

VCC

RLOAD

RP

GND

Figure 15. Output Transient Voltage Protection

BOARD LAYOUT AND GROUNDING

The AD420 ground pin, designated GND, is the high quality

ground reference point for the device. Any external loads on the

REF OUT and VOUT pins of the AD420 should be returned to

this reference point. Analog and digital ground currents should

not share a common path. Each signal should have an appropriate

analog or digital signal return routed close to it. Using this

approach, signal loops enclose a small area, minimizing the

inductive coupling of noise. Wide PC tracks, large gauge wire,

and ground planes are highly recommended to provide low

impedance signal paths.

POWER SUPPLIES AND DECOUPLING

The AD420 supply pins, VCC (Pin 23) and VLL (Pin 2), should be

decoupled to GND with 0.1 μF capacitors to eliminate high

frequency noise that may otherwise get coupled into the analog

system. High frequency ceramic capacitors are recommended.

The decoupling capacitors should be located in close proximity

to the pins and the ground line to have maximum effect. Further

reductions in noise, and improvements in performance, may be

achieved by using a larger value capacitor on the VLL pin.

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