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MX25L2006EM1I12G Datasheet(PDF) 8 Page - Macronix International |
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MX25L2006EM1I12G Datasheet(HTML) 8 Page - Macronix International |
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8 / 50 page  8 P/N: PM1578 MX25L2006E REV.1.5, NOV. 14, 2013 DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended opera- tion. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to follow tCHCL spec. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. The CS# rising time needs to follow tCLCH spec. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 1. 5. For the following instructions: RDID, RDSR, READ, FAST_READ, RDSFDP, DREAD, RES and REMS the shift- ed-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Peripheral Interface Modes Supported SCLK MSB CPHA SI 0 1 CPOL 0 (Serial mode 0) (Serial mode 3) 1 SO SCLK MSB shift in shift out Note: CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is supported. |
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