BR93H56RF-2LB

15/25

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TSZ22111・15・001

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TSZ02201-0R1R0G100260-1-2

Datasheet

Datasheet

27.Feb.2014 Rev.002

4) Write Enable (WEN) / Disable (WDS) Cycle

○At power on, this IC is in Write Disable status by the internal RESET circuit. Before executing the WRITE command, it

is necessary to execute the Write Enable command first. And, once this command is executed, writing is valid unitl the

Write Disable command is executed or the power is turned off.

However, the READ command is valid regardless of

whether Write Enable / Disable command is executed. Input to SK after 6 clocks of this command is available by either

“H” or “L”, but be sure to input it.

○When the Write Enable command is executed after power on, Write Enable status gets in. When the Write Disable

command is executed then, the IC gets in Write Disable status as same as at power on, and then the WRITE command

is canceled thereafter in software manner. However, the READ command is still executable. In Write Enable status, even

when the WRITE command is input by mistake, writing will still continue. To prevent such a mistake, it is recommended

to execute the Write Disable command after the completion of each WRITE execution.

Application

1) Method to cancel each command

○READ

○WRITE, WRAL

Figure 34. READ Cancel Available Timing

Figure 35. WRITE, WRAL Cancel Available Timing

a：From start bit to 27

Cancel by CS=“L”

b：27

Cancellation is not available by any means.

If Vcc is turned OFF in this area,

designated address data is not guaranteed.

Therefore, execute write once again.

c：28

Cancel by CS=“L”

However, when WRITE is started in b area (CS is ended), cancellation is not

available by any means.

And when SK clock is input continuously, cancellation is not available.

Start bit

Ope code

Address

Data

1bit

2bit

8bit

16bit

Cancel is available in all areas in read mode.

●Method to cancel：cancel by CS =“L”

Start bit

Ope code

Address

Data

tE/W

a

1bit

2bit

8bit

16bit

C

b

SK

・Rise of 27

D1

Enlarged figure

D0

DI

26

27

28

29

a

b

c

Note 1)

If Vcc is turned OFF in this area,

designated address data is not guaranteed.

Therefore, it is recommended to execute

WRITE once again.

Note 2)

If CS is started at the same timing as that of

the SK rise, WRITE execution/cancel becomes

unstable.

Therefore, it is recommended to set CS

to “L” in SK=”L” area.

As for SK rise, recommended

CS

1

2

1

5

High-Z

0

0

SK

DI

DO

11

3

4

6

7

8

ENABLE=1

1

DISABLE=0

0

～～

～～

～～

～～

Figure 33. Write Enable (WEN) / Disable (WDS) Cycle