CY7C4255V, CY7C4265V

CY7C4275V, CY7C4285V

Document Number: 38-06012 Rev. *D

Page 6 of 24

Functional Description

The CY7C4255/65/75/85V provides five status pins. These pins

are decoded to determine one of five states: Empty, Almost

Empty, Half Full, Almost Full, and Full (see Table 3 on page 7).

The Half Full flag shares the WXO pin. This flag is valid in the

standalone and width expansion configurations. In the depth

expansion, this pin provides the expansion out (WXO)

information that is used to signal the next FIFO when it is to be

activated.

The Empty and Full flags are synchronous, that is, they change

state relative to either the read clock (RCLK) or the write clock

(WCLK). When entering or exiting the Empty states, the flag is

updated exclusively by the RCLK. The flag denoting Full states

is updated exclusively by WCLK. The synchronous flag

architecture guarantees that the flags remain valid from one

clock cycle to the next. The Almost Empty/Almost Full flags

configurations are fabricated using an advanced 0.35



CMOS technology. Input ESD protection is greater than

2001 V, and latch-up is prevented by the use of guard rings.

Architecture

The

CY7C4255/65/75/85V

consists

of

an

array

of

8K/16K/32K/64K words of 18 bits each (implemented by a dual

port array of SRAM cells), a read pointer, a write pointer, control

signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF,

PAF, FF). The CY7C4255/65/75/85V also includes the control

signals WXI, RXI, WXO, RXO for depth expansion.

Resetting the FIFO

Upon power up, the FIFO must be reset with a Reset (RS) cycle.

This causes the FIFO to enter the Empty condition signified by

EF being LOW. All data outputs go LOW after the falling edge of

RS only if OE is asserted. For the FIFO to reset to its default

state, the user must not read or write while RS is LOW.

FIFO Operation

pins is written into the FIFO on each rising edge of the WCLK

signal. Similarly, when the REN signal is active LOW, data in the

presented on each rising edge of RCLK while REN is active LOW

to be a valid write function.

outputs when OE is deasserted. When OE is enabled (LOW),

on the FIFO that is read enabled.

The FIFO contains overflow circuitry to disallow additional writes

when the FIFO is full, and under flow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

after additional reads occur.

Programming

The CY7C4255/65/75/85V devices contain two 16-bit offset

determine the distance from Empty (Full) that the Almost Empty

(Almost Full) flags become active. If the user elects not to

program the FIFO’s flags, the default offset values are used (see

Table 3 on page 7). When the Load LD pin is set LOW and WEN

offset register on the first LOW-to-HIGH transition of the write

clock (WCLK). When the LD pin and WEN are held LOW then

data is written into the Full offset register on the second

LOW-to-HIGH transition of the write clock (WCLK). The third

transition of the write clock (WCLK) again writes to the Empty

offset register (see Table 2). All offset registers do not have to be

written at one time. One or two offset registers can be written and

then, by bringing the LD pin HIGH, the FIFO is returned to normal

read/write operation. When the LD pin is set LOW, and WEN is

LOW, the next offset register in sequence is written.

The contents of the offset registers can be read on the output

lines when the LD pin is set LOW and REN is set LOW. Then,

data can be read on the LOW-to-HIGH transition of the read

clock (RCLK).

Flag Operation

The CY7C4255/65/75/85V devices provide five flag pins to

indicate the condition of the FIFO contents. Empty and Full are

Full Flag

The Full Flag (FF) goes LOW when device is Full. Write

operations are inhibited whenever FF is LOW regardless of the

state of WEN. FF is synchronized to WCLK, that is, it is

exclusively updated by each rising edge of WCLK.

Empty Flag

The Empty Flag (EF) goes LOW when the device is empty. Read

operations are inhibited whenever EF is LOW, regardless of the

state of REN. EF is synchronized to RCLK, that is, it is

exclusively updated by each rising edge of RCLK.

Table 2. Write Offset Register

LD

WEN

WCLK[1]

Selection

0

0

Writing to offset registers:

Empty Offset

Full Offset

0

1

No Operation

1

0

Write Into FIFO

1

1

No Operation

Note

1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.

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