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CAT93C86U-1.8TE13 Datasheet(PDF) 1 Page - Catalyst Semiconductor |
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CAT93C86U-1.8TE13 Datasheet(HTML) 1 Page - Catalyst Semiconductor |
1 / 9 page 1 CAT93C46/56/57/66/86 1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM FEATURES s High Speed Operation: – 93C46/56/57/66: 1MHz – 93C86: 3MHz s Low Power CMOS Technology s 1.8 to 6.0 Volt Operation s Selectable x8 or x16 Memory Organization s Self-Timed Write Cycle with Auto-Clear s Hardware and Software Write Protection s Power-Up Inadvertant Write Protection s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial and Automotive Temperature Ranges s Sequential Read (except 93C46) s Program Enable (PE) Pin (93C86 only) 93C46/56/57/66/86 F02 PIN CONFIGURATION DIP Package (P) SOIC Package (J) CMOS E2PROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and have a data retention of 100 years. The devices are available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages. DESCRIPTION The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit Serial E2PROM memory devices which are configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46/56/ 57/66/86 are manufactured using Catalyst’s advanced SOIC Package (S) 93C46/56/57/66/86 F01 PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +1.8 to 6.0V Power Supply GND Ground ORG Memory Organization NC No Connection PE* Program Enable BLOCK DIAGRAM Note: When the ORG pin is connected to VCC, the X16 organiza tion is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization. SOIC Package (K) © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice TSSOP Package (U) *Only For 93C86 CS SK DI DO VCC NC (PE*) ORG GND 1 2 3 4 8 7 6 5 CS SK DI DO VCC ORG GND 1 2 3 4 8 7 6 5 VCC CS SK ORG GND DO DI 1 2 3 4 8 7 6 5 CS SK DI DO VCC ORG GND 1 2 3 4 8 7 6 5 NC (PE*) NC (PE*) NC (PE*) 8 7 6 5 VCC ORG GND DI CS SK DO 1 2 3 4 NC (PE*) VCC ADDRESS DECODER MEMORY ARRAY ORGANIZATION DATA REGISTER MODE DECODE LOGIC CLOCK GENERATOR OUTPUT BUFFER DO SK CS DI ORG GND PE* Doc. No. 25056-00 2/98 M-1 |
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