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CAT93C4621 Datasheet(PDF) 8 Page - Catalyst Semiconductor |
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CAT93C4621 Datasheet(HTML) 8 Page - Catalyst Semiconductor |
8 / 10 page 9-92 Advanced Information CAT93CXXXX Stock No. 21084-01 2/98 can then continue to clock in 8-bit (16-bit for x16 format) data to be written to the next higher address. Internally, the address pointer is incremented after each group of eight clocks (16 clocks for x16 format). If the host transmits more than 16 bytes (8 words for x16 format) the address counter ‘wraps around’ and previously transmitted data will be overwritten. After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93CXXXX can be determined by selecting the de- vice and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clock- ing of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93CXXXX can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Figure 5. Erase Instruction Timing Figure 4. Write Instruction Timing SK CS DI DO tCS STANDBY HIGH-Z HIGH-Z 101 AN AN-1 A0 DN D0 BUSY READY STATUS VERIFY tSV tHZ tEW SK CS DI DO STANDBY HIGH-Z HIGH-Z 1 AN AN-1 BUSY READY STATUS VERIFY tSV tHZ tEW tCS 11 A0 |
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