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CAT93CXXXX Datasheet(PDF) 6 Page - Catalyst Semiconductor

Part No. CAT93CXXXX
Description  Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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CAT93CXXXX Datasheet(HTML) 6 Page - Catalyst Semiconductor

 
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Advanced Information
CAT93CXXXX
Stock No. 21084-01 2/98
DEVICE OPERATION
Reset Controller Description
The CAT93CXXXX provides a precision RESET con-
troller that ensures correct system operation during
brown-out and power-up/down conditions. It is config-
ured with open drain RESET outputs. During power-
up, the RESET outputs
remain
active
until
VCC
reaches the VTH threshold and will continue driving the
outputs for approximately 200ms (tPURST) after reach-
ing VTH.
After the tPURST timeout interval, the device
will cease to drive reset outputs. At this point the reset
outputs will be pulled up or down by their respective pull
up/pull down devices. During power-down, the RESET
outputs will begin driving active when VCC falls below
VTH. The RESET outputs will be valid so long as VCC is
>1.0V (VRVALID).
The RESET pins are I/Os; therefore, the CAT93CXXXX
can act as a signal conditioning circuit for an externally
applied reset. The inputs are level triggered; that is, the
RESET input in the 93CXXXX will initiate a reset timeout
after detecting a high and the
RESET input in the
93CXXXX will initiate a reset timeout after detecting a
low.
Watchdog Timer
The Watchdog Timer provides an independent protec-
tion for microcontrollers. During a system failure, the
CAT93CXXXX will respond with a reset signal after a
time-out interval of 1.6 seconds for lack of activity.
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared.
Hardware Data Protection
The 93CXXXX is designed with a VCC lock out data
protection feature to provide a high degree of data
integrity.
The VCC sense provides write protection when VCC falls
below the reset threshold value. The VCC lock out
inhibits writes to the serial EEPROM whenever VCC
falls below (power down) or until VCC reaches the reset
threshold (power up).
Reset Threshold Voltage
From the factory the 93CXXXX is offered in five differ-
ent variations of reset threshold voltages. They are
4.50-4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and
2.55-2.70V.
To provide added flexibility to design
engineers using this product, the 93CXXXX is de-
signed with an additional feature of programming the
reset threshold voltage. This allows the user to change
the existing reset threshold voltage to one of the other
four reset threshold voltages. Once the reset threshold
voltage is selected it will not change even after cycling
the power, unless the user uses the programmer to
change the reset threshold voltage.
However, the
programming function is available only through external
program manufacturers. Please call Catalyst for a list of
programmer manufacturers which support this function.
Memory Functional Description
The CAT93CXXXX is a 1024/2048/4096/16,384-bit non-
volatile memory intended for use with industry standard
microprocessors. The CAT93CXXXX can be organized
as either registers of 16 bits or 8 bits. When organized as
X16, seven 9-bit instructions for 93C46XX; seven 10-bit
instructions for 93C57XX; seven 11-bit instructions for
93C56XX and 93C66XX; seven 13-bit instructions for
93C86XX; control the reading, writing and erase opera-
tions of the device. When organized as X8, seven 10-bit
instructions for 93C46XX; seven 11-bit instructions for
93C57; seven 12-bit instructions for 93C56 and 93C66:
seven 14-bit instructions for 93C86; control the reading,
writing and erase operations of the device. The
CAT93CXXXX operates on a single power supply and
will generate on chip, the high voltage required during
any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit
(93C46XX)//7-bit (93C57XX)/ 8-bit (93C56XX or
93C66XX)/10-bit (93C86XX) (an additional bit when
organized X8) and for write operations a 16-bit data field
(8-bit for X8 organizations).


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