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CAT504JITE13 Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT504JITE13 Datasheet(HTML) 5 Page - Catalyst Semiconductor |
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5 / 12 page  CAT504 5 Doc. No. 25048-0A 2/98 M-1 PIN DESCRIPTION Pin Name Function 1VDD Power supply positive. 2 CLK Clock input pin 3VPP EEPROM Programming Voltage 4 CS Chip Select 5 DI Serial data input pin. 6 DO Serial data output pin. 7 PROG EEPROM Programming Enable Input 8 GND Power supply ground. 9VREFL Minimum DAC output voltage. 10 VOUT4 DAC output channel 4. 11 VOUT3 DAC output channel 3. 12 VOUT2 DAC output channel 2. 13 VOUT1 DAC output channel 1. 14 VREFH Maximum DAC output voltage. DEVICE OPERATION The CAT504 is a quad 8-bit Digital to Analog Converter (DAC) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile EEPROM memory and will not be lost when power is removed from the chip. Upon power up the DACs return to the settings stored in EEPROM memory. Each DAC can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without chang- ing the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT504 employs a standard 3 wire serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DAC address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT504’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DAC control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DAC outputs to the settings stored in EEPROM memory and switches DO to its high imped- ance Tri-State mode. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT504’s clock controls both data flow in and out of the IC and EEPROM memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to EEPROM memory, even though the data being saved may already be resident in the DAC control register. No clock is necessary upon system power-up. The CAT504’s internal power-on reset circuitry loads data from EEPROM to the DACs without using the external clock. As data transfers are edge triggered clean clock transi- tions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic fami- lies work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. DAC addressing is as follows: DAC OUTPUT A0 A1 VOUT1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 |
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