CAT28F102T14R-45T datasheet(5/14 Pages) CATALYST

Part #	CAT28F102T14R-45T

Description	1 Megabit CMOS Flash Memory

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Manufacturer	CATALYST [Catalyst Semiconductor]

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CAT28F102

5

Doc. No. 25038-0A 2/98 F-1

INPUT PULSE LEVELS

REFERENCE POINTS

2.0 V

0.8 V

2.4 V

0.45 V

5108 FHD F04

Note:

(1)

This parameter is tested initially and after a design or process change that affects the parameter.

(2)

Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.

(3)

Input Rise and Fall Times (10% to 90%) < 10 ns.

(4)

Input Pulse Levels = 0.45V and 2.4V. For high speed input pulse levels 0.0V and 3.0V.

(5)

Input and Output Timing Reference = 0.8V and 2.0V. For high speed input and output timing reference=1.5V.

(6)

Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.

(7)

For Load and Reference Points see Figures 3 and 4

(8)

For Load and Reference Points see Figures 1 and 2

1.3V

DEVICE

UNDER

TEST

1N914

3.3K

CL = 100 pF

OUT

CL INCLUDES JIG CAPACITANCE

INPUT PULSE LEVELS

REFERENCE POINTS

2.0 V

0.8 V

2.4 V

0.45 V

5108 FHD F03

Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)

Figure 2. A.C. Testing Load Circuit (example)

Figure 3. High Speed A.C. Testing Input/Output Waveform(3)(4)(5)

JEDEC

Standard

28F102-45(7)

28F102-55(7) 28F102-70 (7) 28F102- 90 (8)

Symbol

Parameter

Min.

Max.

Min. Max. Min.

Max.

Min.

Max

Unit

tAVAV

tRC

Read Cycle Time

45

55

70

90

ns

tELQV

tCE

CE Access Time

45

55

70

90

ns

tAVQV

tACC

Address Access Time

45

55

70

90

ns

tGLQV

tOE

OE Access Time

20

25

28

35

ns

tAXQX

tOH

Output Hold from Address

0

ns

OE/CE Chan

tGLQX

tOLZ(1)(6) OE to Output in Low-Z

0

ns

tELQX

tLZ(1)(6)

CE to Output in Low-Z

0

ns

tGHQZ

tDF(1)(2)

OE High to Output High-Z

15

18

20

ns

tEHQZ(1)(2)

-

CE High to Output High-Z

15

25

30

ns

tWHGL

Write Recovery Time Before

6

µs

Read

3V

0.0

A.C. CHARACTERISTICS, Read Operation

1.3V

DEVICE

UNDER

TEST

1N914

3.3K

CL = 100 pF

OUT

CL INCLUDES JIG CAPACITANCE

Figure 4. High Speed A.C. Testing Load Circuit (example)

V

CC = +5V ±10%, unless otherwise specified

1.5V

Vcc=5V+5%

30

Vcc=5V+5%

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