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CAT25C03 Datasheet(PDF) 6 Page - Catalyst Semiconductor |
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CAT25C03 Datasheet(HTML) 6 Page - Catalyst Semiconductor |
6 / 10 page 6 CAT25C03/05/09/17/33 Doc. No. 25068-00 2/98 Advanced After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continu- ing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefi- nitely. The read operation is terminated by pulling the CS high. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. If a non-volatile write is in progress, the RDSR instruction returns a high on SO. When the non-volatile write cycle is completed, the status register data is read out. Figure 2. WREN Instruction Timing Figure 3. WRDI Instruction Timing SK SI CS SO 0 0 0 0 010 0 HIGH-Z 25C128 F05 DEVICE OPERATION Write Enable and Disable The CAT25C03/05/09/17/33 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C03/05/09/17/33, followed by the 16-bit address for 25C09/17/33 (only 10- bit addresses are used for 25C09, 11-bit addresses are used for 25C17, and 12-bit addresses are used for 25C33. The rest of the bits are don't care bits) and 8-bit address for 25C03/05 (for the 25C05, bit 3 of the read data instruction contains address A8). SK SI CS SO 00000 110 HIGH-Z |
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