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CAT24C44 Datasheet(PDF) 5 Page - Catalyst Semiconductor

Part No. CAT24C44
Description  256-Bit Serial Nonvolatile CMOS Static RAM
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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CAT24C44 Datasheet(HTML) 5 Page - Catalyst Semiconductor

   
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CAT24C44
5
Doc. No. 25019-0A 2/98 N-1
DEVICE OPERATION
The CAT24C44 is intended for use with standard micro-
processors. The CAT24C44 is organized as 16 registers
by 16 bits. Seven 8-bit instructions control the device’s
operating modes, the RAM reading and writing, and the
E2PROM storing and recalling. It is also possible to
control the E2PROM store and recall functions in hard-
ware with the
STORE and RECALL pins. The CAT24C44
operates on a single 5V supply and will generate, on
chip, the high voltage required during a RAM to E2PROM
storing operation.
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin remains in a high impedance state except when
outputting data from the device. The
CE (Chip Enable)
pin must remain high during the entire data transfer.
The format for all instructions sent to the CAT24C44 is
a logical ‘1’ start bit, 4 address bits (data read or write
operations) or 4 “Don’t Care” bits (device mode opera-
tions), and a 3-bit op code (see Instruction Set). For data
write operations, the 8-bit instruction is followed by 16
bits of data. For data read instructions, DO will come out
of the high impedance state and enable 16 bits of data
to be clocked from the device. The 8th bit of the read
instruction is a “Don’t Care” bit. This is to eliminate any
bus contention that would occur in applications where
the DI and DO pins are tied together to form a common
DI/DO line. A word of caution while clocking data to and
from the device: If the
CE pin is prematurely deselected
while shifting in an instruction, that instruction will not be
executed, and the shift register internal to the CAT24C44
will be cleared. If there are more than or less than 16
clocks during a memory data transfer, an improper data
transfer will result. The SK clock is completely static
allowing the user to stop the clock and restart it to
resume shifting of data.
Read
Upon receiving a start bit, 4 address bits, and the 3-bit
read command (clocked into the DI pin), the DO pin of
the CAT24C44 will come out of the high impedance state
and the 16 bits of data, located at the address specified
in the instructions, will be clocked out of the device.
When clocking data from the device, the first bit clocked
out (DO) is timed from the falling edge of the 8th clock,
all succeeding bits (D1–D15) are timed from the rising
edge of the clock.
Write
After receiving a start bit, 4 address bits, and the 3-bit
WRITE command, the 16-bit word is clocked into the
device for storage into the RAM memory location speci-
fied. The
CE pin must remain high during the entire write
operation.
Figure 1. RAM Read Cycle Timing
5157 FHD F02
Note:
(1) Bit 8 of READ instruction is “Don’t Care”.
Figure 2. RAM Write Cycle Timing
5157 FHD F03
SK
CE
DI
D0
1
234
56789
10
11
12
22
23
24
1
D1
D2
D3
D13
D14
D15
A1
1
AAA
0
SK
CE
DI
DO
HIGH-Z
D0
1
234
56789
10
11
12
22
23
24
1
D1
D2
D3
D14
D15
D0
AX
11
AAA
(8)
(1)


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