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LP8900TLE-AAEC Datasheet(PDF) 2 Page - Texas Instruments |
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LP8900TLE-AAEC Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page Top View Bottom View B1 GND VOUT 1 A2 VIN B2 VOUT 2 C2 A1 VEN 1 B1 GND C1 VEN 2 VOUT 2 C2 VOUT 1 A2 C1 VEN 2 A1 VEN 1 VIN B2 LP8900 SNVS542C – MAY 2008 – REVISED JULY 2013 www.ti.com Pin Descriptions Pin No. Symbol Name and Function A1 VEN 1 Enable Input; Enables the Regulator when ≥ 1.2V. Disables the Regulator when ≤ 0.4V. Enable Input has an internal 3-M Ω pull-down resistor to GND. B1 GND Common Ground. C1 VEN 2 Enable Input; Enables the Regulator when ≥ 1.2V. Disables the Regulator when ≤ 0.4V. Enable Input has an internal 3-M Ω pull-down resistor to GND. C2 VOUT 2 Voltage output. A Low ESR Ceramic Capacitor should be connected from this pin to GND. (See Application Information) Connect this output to the load circuit. B2 VIN Voltage Supply Input. A 1.0 µF capacitor should be connected from this pin to GND. A2 VOUT 1 Voltage output. A Low ESR Ceramic Capacitor should be connected from this pin to GND. (See Application Information) Connect this output to the load circuit. Table 1. Device Voltage Options Base Part Number VOUT1 VOUT2 LP8900TLE-3333 2.8V 2.8V LP8900TLE-AAAH 2.7V 2.7V LP8900TLE-AAEB 2.8V 2.7V LP8900TLE-AAEC 2.8V 1.2V Connection Diagram Figure 1. 6-Bump Thin DSBGA, Large Bump See package number YZR0006CZA This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LP8900 |
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