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EP1K10TC100-3N Datasheet(PDF) 48 Page - Altera Corporation |
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EP1K10TC100-3N Datasheet(HTML) 48 Page - Altera Corporation |
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48 / 86 page  48 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial- and extended-temperature-range devices. (4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. (5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (6) Typical values are for TA = 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 V or 3.3 V. (7) These values are specified under the ACEX 1K Recommended Operating Conditions shown in Table 19 on page 46. (8) The ACEX 1K input buffers are compatible with 2.5-V, 3.3-V (LVTTL and LVCMOS), and 5.0-V TTL and CMOS signals. Additionally, the input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 22. (9) The IOH parameter refers to high-level TTL, PCI, or CMOS output current. (10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins as well as output pins. (11) This value is specified for normal device operation. The value may vary during power-up. (12) This parameter applies to -1 speed grade commercial temperature devices and -2 speed grade industrial and extended temperature devices. (13) Pin pull-up resistance values will be lower if the pin is driven higher than VCCIO by an external source. (14) Capacitance is sample-tested only. Table 21. ACEX 1K Device Capacitance Note (14) Symbol Parameter Conditions Min Max Unit CIN Input capacitance VIN = 0 V, f = 1.0 MHz 10 pF CINCLK Input capacitance on dedicated clock pin VIN = 0 V, f = 1.0 MHz 12 pF COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 10 pF |
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