©2000 California Micro Devices Corp. All rights reserved.

7/21/2000

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

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CSPDDR100

CALIFORNIA MICRO DEVICES

Applications

The CSPDDR100, Chip Scale DDR Termination Array,

provides sixteen (16) channels of series/parallel termi-

nation for SSTL termination applications such as DDR

memory systems. SSTL is the bus standard for DDR

SDRAM systems. Applying terminating resistors to DDR

SDRAM’s interconnections is a necessity to avoid signal

integrity problems in the memory system’s operation.

Improper or no termination on an interconnection that is

a transmission line will cause reflections which in turn

will affect the performance of the system due to ringing,

delays, exceeding IC voltage specifications, or

crosstalk. [1]

SSTL has four possible configurations. One of them

calls for both a series termination resistor and a parallel

termination at one end of the bus, as shown in Figure 1.

This is the application that the CSPDDR100 satisfies.

When a full level signal is sent down the transmission

line and no reflection is desired, the parallel load

resistance should equal the characteristic impedance

(Z

signal is sent down a transmission line, it is desirable to

have an intentional mismatch of the parallel termination

load resistor so that the higher level reflection voltage

(resulting from having R

full signal level so that load switching occurs in only one

propagation delay time. The use of a series termination

resistor at the source enables the sending of a reduced

level signal on the first incident wave. A reduced level

signal is beneficial in reducing rise times and EMI.

The values of the resistors for DDR/SSTL terminations

are user determined. If values different from the ones in

the CSPDDR100 specification are desired, please

contact California Micro Devices for quotations on other

values.

[1] James Sutherland, “Understanding Transmission Lines, and

High Speed Terminations”, EDN, October 9, 1999

Figure 1. SSTL_2 Class II,

Symmetrically Double Parallel Terminated Output Load with Series Resistor

+

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