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OR2T40A-5BA304 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers |
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OR2T40A-5BA304 Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 192 page Data Sheet ORCA Series 2 FPGAs June 1999 6 Lucent Technologies Inc. Programmable Logic Cells (continued)) Key: C = controlled by configuration RAM. Figure 3. Simplified PFU Diagram 5-4573(F) A4 A3 A2 A1 A4 A3 A2 A1 QLUT3 A0 CARRY CARRY A3 A2 A1 A0 QLUT2 B4 B3 B2 B1 B4 B3 B2 B1 QLUT1 B0 CARRY CARRY B3 B2 B1 B0 QLUT0 CIN C0 LSR GSR WD[3:0] CK CKEN TRI PFU_XOR B4 A4 PFU_NAND PFU_MUX C C C C WD3 WD2 WD1 WD0 C C C T T T T REG3 SR EN REG2 SR EN REG1 SR EN REG0 SR EN O4 O3 O2 O1 O0 F3 C C COUT F2 F1 F0 D0 D1 D2 D3 Q0 Q1 Q2 Q3 C T T T T C Figure 2 and Figure 3 show high-level and detailed views of the ports in the PFU, respectively. The ports are referenced with a two- to four-character suffix to a PFU’s location. As mentioned, there are two 5-bit input data buses (A[4:0] and B[4:0]) to the LUT, one 4-bit input data bus (WD[3:0]) to the latches/FFs, and an output data bus (O[4:0]). Figure 3 shows the four latches/FFs (REG[3:0]) and the 64-bit look-up table (QLUT[3:0]) in the PFU. The PFU does combinatorial logic in the LUT and sequential logic in the latches/FFs. The LUT is static random access memory (SRAM) and can be used for read/ write or read-only memory. The eight 3-state buffers found in each PLC are also shown, although they actu- ally reside external to the PFU. Each latch/FF can accept data from the LUT. Alterna- tively, the latches/FFs can accept direct data from WD[3:0], eliminating the LUT delay if no combinatorial function is needed. The LUT outputs can bypass the latches/FFs, which reduces the delay out of the PFU. It is possible to use the LUT and latches/FFs more or less independently. For example, the latches/FFs can be used as a 4-bit shift register, and the LUT can be used to detect when a register has a particular pattern in it. |
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