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PCM55JP Datasheet(PDF) 7 Page - Burr-Brown (TI) |
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PCM55JP Datasheet(HTML) 7 Page - Burr-Brown (TI) |
7 / 7 page ® PCM54/55 7 Due to the fast settling time of the PCM54-V, it is possible to minimize the delay between the left channel and right channel outputs when using a single D/A converter for both channels. This is important because the left and right chan- nel data is recorded in phase and use of a slower D/A converter would result in significant phase error at the higher audio frequencies. A low-pass filter is required at the S/H output to remove all unwanted frequency components caused by the sampling frequency as well as the discrete nature of the D/A converter output. The filter must have a flat amplitude response over the entire audio band (0 to 20kHz) and a very high attenu- ation above 20kHz. Most previous digital audio circuits used a high-order (9-13 pole) analog filter. However, the phase response of an analog filter with these amplitude character- istics is nonlinear and can disturb the pulse-shaped charac- teristics of the transients contained in music. INSTALLATION CONSIDERATIONS If the optional external MSB error circuitry is used (PCM54), a potentiometer with adequate resolution and a TCR of 100ppm/ °C or less is required. Also, extra care must be taken to insure that no leakage path (either AC or DC) exists to pin 27 (PCM54). If circuit is not used, pin 1 (PCM54) should be terminated to common with a 0.01 µF capacitor. The PCM converter and the wiring to its connectors should be located to provide the optimum isolation from sources of RFI and EMI. The important consideration in the elimina- tion of RF radiation or pickup is loop area; therefore, signal leads and their return conductors should be kept close together. This reduces the external magnetic field along with any radiation. Also, if a signal lead and its return conductor are wired close together, they represent a small flux-capture cross section for any external field. This reduces radiation pickup in the circuit. APPLICATIONS A sample/hold amplifier, or “deglitcher”, is required at the output of the D/A converter for both the left and right channel, as shown in Figure 7. The S/H amplifier for the left channel is composed of A 2, SW1, and associated circuitry. A2 is used as an integrator to hold the analog voltage in C 1. Since the source and drain of the FET switch operates at a virtual ground when “C” and “B” are closed in the simple mode, there is no increase in distortion caused by the modulation effect of R ON by the audio signal. Figure 8 shows the deglitcher control signals for both the left and right channels which are produced by the timing control logic. A delay of 2.5 µs (tω) is provided to eliminate the glitch and allow the output of the PCM54-V to settle within a small error band around its final value before connecting it to the channel output. PCM54/55 A 1 C 1 C A B SW 1 Left Channel Output to LPF and Other Circuits Left Channel Deglitcher Control RR RR A 2 C 2 C A B SW 2 Right Channel Output to LPF and Other Circuits A 1, A2 ATE OPA101 or OPA404 Right Channel Deglitcher Control Data to DAC A LOW signal on the deglitcher control closes switch “A”, while a HIGH signal closes switch “B”. FIGURE 7. A Sample/Hold Amplifier (deglitcher) is Re- quired at the Digital-to-Analog Output for Both Left and Right Channels. Right Channel Data N Left Channel Data N Right Channel Data N+1 Left Channel Data N+1 44.1kHz Delay Between Left and Right Channel Data for DAC Right Channel Deglitcher Control Left Channel Deglitcher Control The deglitcher control signals are generated by the timing control logic. The fast settling time of the PCM54/55 makes it possible to minimize the delay between left and right channels to approximately 4.5 µs which reduces phase error at the higher audio frequencies. t S t W FIGURE 8. Timing Diagram for the Deglitcher Control Signals. |
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