7

®

PCM56

FIGURE 7. Input Timing Diagram.

FIGURE 8. Input Timing Relationships.

source and drain of the FET switch operate at a virtual

ground when “C” and “B” are connected in the sample

mode, there is no increase in distortion caused by the

Figure 10 shows the deglitcher controls for both left and

right channels which are produced by timing control logic.

A delay of 1.5

µs (t

ω) is provided to allow the output of the

PCM56 to settle within a small error band around its final

value before connecting it to the channel output. Due to the

fast settling time of the PCM56 it is possible to minimize the

delay between the left- and right-channel outputs when

using a single D/A converter for both channels. This is

important because the right- and left-channel data are recorded

in-phase and the use of the slower D/A converter would

result in significant phase error at higher frequencies.

The obvious solution to the phase shift problem in a two-

channel system would be to use two D/A converters (one per

channel) and time the outputs to change simultaneously.

Figure 11 shows a block diagram of the final test circuitry

used for PCM56. It should be noted that no deglitching

circuitry is required on the DAC output to meet specified

THD performance. This means that when one PCM56 is

used per channel, the need for all the sample/hold and

controls circuitry associated with a single DAC (two-channel)

design is effectively eliminated. The PCM56 is tested to

meet its THD specifications without the need for output

deglitching.

A low-pass filter is required after the PCM56 to remove all

unwanted frequency components caused by the sampling

frequency as well as those resulting from the discrete nature

of the D/A output. This filter must have a flat frequency

response over the entire audio band (0-20kHz) and a very

high attenuation above 20kHz.

Most previous digital audio circuits used a higher order (9-

13 pole) analog filter. However, the phase response of an

analog filter with these amplitude characteristics is nonlinear

and can disturb the pulse-shaped characteristic transients

contained in music.

of RF radiation or pickup is loop area; therefore, signal leads

and their return conductors should be kept close together.

This reduces the external magnetic field along with any

radiation. Also, if a signal lead and its return conductor are

wired close together, they represent a small flux-capture

cross section for any external field. This reduces radiation

pickup in the circuit.

APPLICATIONS

Figures 9 and 10 show a circuit and timing diagram for a

single PCM56 used to obtain both left- and right-channel

output in a typical digital audio system. The audio output of

the PCM56 is alternately time-shared between the left and

right channels. The design is greatly simplified because the

PCM56 is a complete D/A converter requiring no external

reference or output op amp.

A sample/hold (S/H) amplifier, or “deglitcher” is required at

the output of the D/A for both the left and right channel, as

shown in Figure 9. The S/H amplifier for the left channel is

Data

Latch

Enable

2

(2)

Clock

(3)

MSB

LSB

MSB

(4)

(1)

NOTES: (1) If clock is stopped between input of 16-bit data words, latch enable (LE) must remain low until after the first clock of the next 16-bit data

word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch

enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going

negative.

1

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

MSB

Data

Input

> 40ns

> One Clock Cycle

Latch

Enable

> One Clock Cycle

Clock

Input

> 40ns

> 5ns

> 100ns

> 15ns

LSB

>15ns >15ns

> 40ns