®

10

PCM1717

DIN (pin 5)

DIN (pin 5)

Audio Data Word = 16-Bit

LRCIN (pin 4)

BCKIN (pin 6)

16

14

MSB

LSB

MSB

LSB

Left-channel Data

Right-channel Data

1 f/s

15

16

12

3

16

14

15

12

3

14

15

Audio Data Word = 18-Bit

18

16

MSB

LSB

MSB

LSB

17

18

12

3

18

16

17

12

3

16

17

FIGURE 5. “Normal” Data Input Timing.

DIN (pin 5)

DIN (pin 5)

Audio Data Word = 16-Bit

LRCIN (pin 4)

BCKIN (pin 6)

16

14

MSB

LSB

MSB

LSB

Left-channel Data

Right-channel Data

1 f/s

15

12

3

16

14

15

12

3

Audio Data Word = 18-Bit

18

16

MSB

LSB

MSB

LSB

17

12

3

18

16

17

12

3

12

12

t

BCH

t

BCL

t

LB

t

BCY

t

BL

t

DH

t

DS

50% of V

DD

50% of V

DD

50% of V

DD

LRCIN

BCKIN

DIN

BCKIN Pulsewidth (High Level)

50ns (min)

BCKIN Pulsewidth (Low Level)

50ns (min)

BCKIN Pulse Cycle Time

100ns (min)

BCKIN Rising Edge ¨ LRCIN Edge

30ns (min)

LRCIN Edge ¨ BCKIN Rising Edge

30ns (min)

DIN Setup Time

30ns (min)

DIN Hold Time

30ns (min)

FIGURE 7. Data Input Timing.

Bit 1 is used to select the polarity of LRCIN (sample rate

clock). When bit 1 is LOW, a HIGH state on LRCIN is used

for the left channel, and a LOW state on LRCIN is used for

the right channel. When bit 1 is HIGH the polarity of LRCIN

is reversed.

Bit 2 is used to select the input word length. When bit 2 is

LOW, the input word length is set for 16 bits; when bit 2 is

HIGH, the input word length is set for 18 bits.

Bit 3 is used as an attenuation control. When bit 3 is set

HIGH, the attenuation data on Register 0 is used for both

channels, and the data in Register 1 is ignored. When bit 3

is LOW, each channel has separate attenuation data.

Bits 4 through 7 are used to determine the output format, as

shown in Table V:

PL0

PL1

PL2

PL3

Lch OUTPUT

Rch OUTPUT

NOTE

0

0

0

0

MUTE

MUTE

MUTE

0

0

0

1

MUTE

R

0

0

1

0

MUTE

L

0

0

1

1

MUTE

(L + R)/2

0

1

0

0

R

MUTE

01

0

1

R

R

0

1

1

0

R

L

REVERSE

0

1

1

1

R

(L + R)/2

1

0

0

0

L

MUTE

1

0

0

1

L

R

STEREO

10

1

0

L

L

1

0

1

1

L

(L + R)/2

1

1

0

0

(L + R)/2

MUTE

1

1

0

1

(L + R)/2

R

1

1

1

0

(L + R)/2

L

1

1

1

1

(L + R)/2

(L + R)/2

MONO

TABLE V. PCM1717 Output Mode Control.

REGISTER RESET STATES

After reset, each register is set to a predetermined state:

Register 0

0000 0000 1111 1111

Register 1

0000 0010 1111 1111

Register 2

0000 0100 0000 0000

Register 3

0000 0110 1001 0000