®

9

OPA549

FIGURE 2. Adjustable Current Limit.

ENABLE/STATUS (E/S) PIN

The Enable/Status Pin provides two unique functions:

1) output disable by forcing the pin low and 2) thermal

shutdown indication by monitoring the voltage level at the

pin. Either or both of these functions can be utilized in an

application. For normal operation (output enabled), the E/S

pin can be left open or driven high (at least 2.4V above Ref).

A small value capacitor connected between the E/S pin and

Output Disable

To disable the output, the E/S pin is pulled to a logic low

(no greater than 0.8V above Ref). Typically the output is

shut down in 1

µs. To return the output to an enabled state,

the E/S pin should be disconnected (open) or pulled to at

least 2.4V above Ref. It should be noted that driving the E/

S pin high (output enabled) does not defeat internal ther-

mal shutdown; however, it does prevent the user from

monitoring the thermal shutdown status. See Figure 3 for

an example implementing this function.

This function not only conserves power during idle periods

(quiescent current drops to approximately 6mA) but also

allows multiplexing in multi-channel applications. Figure 12

shows two OPA549s in a switched amplifier configuration.

The on/off state of the two amplifiers is controlled by the

voltage on the E/S pin. Under these conditions, the disabled

device will behave like a 750pF load. Slewing faster than

3V/

µs will cause leakage current to rapidly increase in

devices that are disabled, and will contribute additional load.

At high temperature (125

°C), the slewing threshold drops to

approximately 2V/

µs. Input signals must be limited to avoid

excessive slewing in multiplexed applications.

FIGURE 3. Output Disable.

OPA549

E/S

CMOS or TTL

Ref

Logic

Ground

7500

Ω

R

CL

0.01

µF

(optional, for noisy

environments)

8

6

8

6

4.75V

R

– 7500

Ω

OPA549 CURRENT LIMIT: 0A to 10A

NOTES: (1) Resistors are nearest standard 1% values. (2) Offset in the current limit circuitry

may introduce approximately

±0.25A variation at low current limit values.

DESIRED

CURRENT LIMIT

2.5A

3A

4A

5A

6A

7A

8A

9A

10A

(R

I

22.6k

Ω

17.4k

Ω

11.3k

Ω

7.5k

Ω

4.99k

Ω

3.24k

Ω

1.87k

Ω

845

Ω

I

CURRENT

(I

0

µA

158

µA

190

µA

253

µA

316

µA

380

µA

443

µA

506

µA

570

µA

633

µA

VOLTAGE

(V

(Ref) + 4.75V

(Ref) + 3.56V

(Ref) + 3.33V

(Ref) + 2.85V

(Ref) + 2.38V

(Ref) + 1.90V

(Ref) + 1.43V

(Ref) + 0.95V

(Ref) + 0.48V

(Ref)

(a) RESISTOR METHOD

15800 (4.75V)

I

LIM

=

– 7.5k

Ω

75k

Ω

I

LIM

7500

Ω

I

V

(b) DAC METHOD (Current or Voltage)

D/A

I

SET

4.75V

Ref

Ref

±I

Max I

(4.75) (15800)

7500

Ω + R

CL

Max I

±I