4

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DSD1700

GENERAL INFORMATION

The DSD1700 is designed solely for use in DSD and SACD

applications. It is not compatible with standard CD audio

transports, or DVD/MPEG-2 decoders. Burr-Brown manu-

facturers a wide array of products for these applications.

Please refer to our audio brochure and product data sheets,

available from our web site (www.burr-brown.com) and

local sales offices.

FUNCTIONAL DESCRIPTION

The concept of Direct Stream Digital (DSD) conversion is

simple. An analog audio input is digitized by a 1-bit, 64x

oversampled delta-sigma modulator. The 1-bit data stream is

then stored and may be transferred to a SACD disc at a later

time. For playback, the 1-bit, 64x oversampled data is then

presented to the DSD1700 directly by a DSD decoder IC.

The DSD1700 then low-pass filters the oversampled data to

reconstruct the original analog audio waveform. The record-

ing and playback functions are illustrated in Figures 1 and 2

respectively.

To perform the digital-to-analog conversion, the DSD1700

includes both the decoder interface logic and an analog FIR

filter. The following paragraphs provide a summary of these

functions.

FIGURE 1. DSD Recording.

FIGURE 2. DSD Playback.

DECODER INTERFACE

The decoder interface consists of several CMOS logic in-

puts. The system clock input, SCK (pin 28), operates at

11.2896MHz (256 • 44.1kHz). The data bit clock, DCK

(pin 27), operates at 2.8244 MHz (64 • 44.1kHz) and is the

64x oversampled data clock. The 1-bit, 64x oversampled

data stream is input at DATA (pin 26). DATA and DCK are

synchronized to the SCK falling edge.

The DSD1700 generates HOT and COLD data internally for

use with the double differential analog FIR filter. The

PHASE input (pin 4) is used to determine the polarity of the

HOT and COLD data (normal or inverted). The PHASE

input is synchronized to the rising edge of SCK.

The RST input (pin 3) is used for system reset purposes.

RST should be High for normal operation, and Low for reset

operation. When RST is held Low, the current outputs of the

analog FIR filter are set to the bipolar zero (BPZ) level. The

RST signal is synchronized to the rising edge of SCK.

TIMING

Figures 3 though 6 show the timing diagrams for the

DSD1700 interface signals. Figure 3 shows the system clock

(SCK) timing requirements. Figure 4 shows the general

timing for the data input. Figures 5 and 6 show the detailed

timing for the DSD data and control data inputs.

LOGIC

DSD

Input

(64f

Analog

Output

Low-Pass

Filter

Interface

Logic

FIGURE 3. System Clock Timing.

FIGURE 4. Input Signal Timing.

t

SCKH

t

SCKL

1/256 f

S

V

IH

V

IL

High

Low

System Clock

V

V

∫

Q

Analog

Input

DSD

Output

(64f

Loop Filter

(Noise Shaping

and Integration)

1-Bit

Quantizer

+

–

DATA

SCK (256f

DCK (64f

RST

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

System Clock Pulse Width High

10

ns

System Clock Pulse Width Low

10

ns