®

DDC101

6

PIN CONFIGURATION

Top View

24-Lead SOIC

SECTION 3

PIN DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

REFERENCE BUFFER BYPASS

V

REF

TEST In

RESET SETUP In

SETUP

READ DATA/SETUP

DATA TRANSMIT In

OVERFLOW + Out

OVERFLOW – Out

DATA VALID Out

DATA OUTPUT

DIGITAL GROUND

V

ANALOG COMMON

ANALOG In

ANALOG COMMON

V

V

RESET SYSTEM In

FDS (Final Data Point Start) In

SYSTEM CLOCK

DATA CLOCK

DATA INPUT

V

PIN

NUMBER

NAME

DESCRIPTION

Negative analog power supply voltage, –5VDC.

2

ANALOG COMMON

Analog ground point.

3

ANALOG INPUT

Input for low level current signal. Photosensor can be directly connected to this input. With a resistor in series,

DDC101 will convert a voltage input.

4

ANALOG COMMON

Analog ground point.

Positive analog power supply voltage, +5VDC. Hardwire to pin 6.

Positive analog power supply voltage, +5VDC. Hardwire to pin 5.

7

RESET SYSTEM In

This input resets DDC101, but does not reset the SETUP register. The DDC101 system is reset when this pin

is active; reset action is removed when the pin is inactive.

8

FDS In

This is Final Data point Start input. This input is the basic user control of the integration and conversion timing.

When it becomes active, the DDC101 starts collection of the M, final data point samples. The beginning of the

next integration time is exactly M system clock periods after the Final Data point Start command when operating

in the continuous mode.

9

SYSTEM CLOCK

This clock input sets the basic sampling rate of the DDC101. The DDC101 is specified with a clock speed of

2MHz. The clock speed can be 0.5MHz to 2.0MHz.

10

DATA CLOCK

This clock input controls the data transfer rate for the serial DATA INPUT and DATA OUTPUT ports. The DATA

CLOCK is independent of the SYSTEM CLOCK. This allows the DATA CLOCK to be operated at higher or lower

speeds than the SYSTEM CLOCK. For best noise performance, data should not be transmitted and the DATA

CLOCK should not be active during the initial and final data point collection. If data is being transmitted during

the initial and final data point collection periods, the DATA CLOCK should be synchronized to the SYSTEM

CLOCK, to minimize added noise. DATA CLOCK can be connected to SYSTEM CLOCK, so that the same clock

is used for both; however, for best noise performance, the DATA CLOCK input should be active only when data

is transmitted.

11

DATA INPUT

This input can be used to “daisy chain” the output of several DDC101s together to minimize wiring. The output

register of the DDC101 acts as a shift register to pass through the output of previously connected DDC101 units.

In this way, multiple DDC101 units can convert simultaneously then sequence the data out serially on the same

data line with one common control line and one common data line for all DDC101 units.

12

V

13

DIGITAL GROUND

Digital ground point.

14

DATA OUTPUT

This output provides serial digital data clocked out at user controlled DATA CLOCK rate. Output data format

is a 21-bit Binary Two's Complement word or a 20-bit Straight Binary word. The data word is transmitted MSB

first. When DATA TRANSMIT is not active DATA OUTPUT tri-states.

15

DATA VALID

This output is activated when conversion is complete and remains active until the DATA TRANSMIT input is

activated.

16

OVERFLOW–

The OVERFLOW output signals each provide an open collector output so that the overflow outputs from several

17

OVERFLOW+

DDC101s can easily be connected (wire ORed) together to a common pull-up resistor. They are activated when

the input is beyond the acceptable range during conversion. Specifically, they are activated when the internal

D/A converter input or digital filter exceeds full scale. They are Cleared at the end of conversion 1/2 clock cycle

after DATA VALID high. DATA VALID can be used to capture OVERFLOW data into an external register.