5

®

DAC811

FIGURE 1. Power Supply Rejection vs Power Supply Ripple

Frequency.

OPERATION

DAC811 is a complete single IC chip 12-bit D/A converter.

The chip contains a 12-bit D/A converter, voltage reference,

output amplifier, and microcomputer-compatible input logic

as shown in Figure 2.

INTERFACE LOGIC

Input latches A, B, and C hold data temporarily while a

complete 12-bit word is assembled before loading into the

D/A register. This double-buffered organization prevents the

generation of spurious analog output values. Each register is

independently addressable.

logic 1, the input data is latched into the input registers and

FIGURE 2. DAC811 Block Diagram.

WR

LDAC

OPERATION

1

X

X

X

X

No operation

0

0

1

1

1

Enables input latch 4MSBs

0

1

0

1

1

Enables input latch 4 middle bits

0

1

1

0

1

Enables input latch 4LSBs

01

1

1

0

Loads D/A latch from input latches

0

0

0

0

0

Makes all latches transparent

“X” = Don’t care.

TABLE II. DAC813 Interface Logic Truth Table.

GAIN AND OFFSET ADJUSTMENTS

Figures 3 and 4 illustrate the relationship of offset and gain

adjustments to unipolar and bipolar D/A converter output.

OFFSET ADJUSTMENT

For unipolar (USB) configurations, apply the digital input

code that should produce zero voltage output, and adjust the

offset potentiometer for zero output. For bipolar (BOB,

BTC) configurations, apply the digital input code that should

produce the maximum negative output voltage and adjust

the offset potentiometer for minus full scale voltage. Ex-

ample: If the full scale range is connected for 20V, the

maximum negative output voltage is –10V. See Table III for

corresponding codes.

The D/A latch is controlled by LDAC and WR. LDAC and

WR are internally NORed so that the latches transmit data to

the D/A switches when both LDAC and WR are at logic 0.

When either LDAC or WR are at logic 1, the data is latched

in the D/A latch and held until LDAC and WR go to logic 0.

All latches are level-triggered. Data present when the con-

trol signals are logic 0 will enter the latch. When any one of

the control signals returns to logic 1, the data is latched.

Table II is a truth table for all latches.

Frequency (Hz)

1

0.1

0.01

0.001

0.0001

10

100

1k

10k

100k

+V

CC

–V

CC

V

DD

M

1

D0

BPO

SJ

V

OUT

12-Bit D/A Converter

12-Bit D/A Latch

4-Bit Latch, A

27

26

25

24

7

8

9

10

11

12

13

14

19

18

17

16

D11

D8

D7

Reference

2

WR

4

A

5

6

LDAC

3

10V

Range

N

B

N

C

N

D4

D3

ACOM

23

Ref Out

28

R

BPO

R

F

R

F

4-Bit Latch, B

4-Bit Latch, C

MSB

LSB